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參數(shù)資料
| 型號： | NT5DS64M4AT |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 256Mb DDR333/300 SDRAM |
| 中文描述： | 256Mb的DDR333/300內(nèi)存 |
| 文件頁數(shù)： | 9/27頁 |
| 文件大小： | 269K |
| 代理商： | NT5DS64M4AT |
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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb DDR333/300 SDRAM
Preliminary
10/01
9
NANYA TECHNOLOGY CORP
. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Notes:
1. For a burst length of two, A1-A i selects the two-data-element block; A0 selects the first access within the block.
2. For a burst length of four, A2-A i selects the four-data-element block; A0-A1 selects the first access within the block.
3. For a burst length of eight, A3-A i selects the eight-data- element block; A0-A2 selects the first access within the block.
4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type
and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the burst type and the start-
ing column address, as shown in
Burst Definition
on page 9.
Read Latency
The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a Read command and the availability
of the first burst of output data. The latency can be programmed 2 or 2.5 clocks.
If a Read command is registered at clock edge n, and the latency is
m
clocks, the data is available nominally coincident with
clock edge
n +
m.
Reserved states should not be used as unknown operation or incompatibility with future versions may result.
Burst Definition
Burst Length
Starting Column Address
Order of Accesses Within a Burst
A2
A1
A0
Type = Sequential
Type = Interleaved
2
0
0-1
0-1
1
1-0
1-0
4
0
0
0-1-2-3
0-1-2-3
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
2-3-0-1
1
1
3-0-1-2
3-2-1-0
8
0
0
0
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7
0
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
0
1
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
0
4-5-6-7-0-1-2-3
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1
1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| NT5DS64M4AT-6 | 256Mb DDR333/300 SDRAM |
| NT5DS64M4AT-66 | 256Mb DDR333/300 SDRAM |
| NT5DS64M4AW | 256Mb DDR333/300 SDRAM |
| NT5DS64M4AW-6 | 256Mb DDR333/300 SDRAM |
| NT5DS64M4AW-66 | 256Mb DDR333/300 SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NT5DS64M4AT-6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:256Mb DDR333/300 SDRAM |
| NT5DS64M4AT-66 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:256Mb DDR333/300 SDRAM |
| NT5DS64M4AT-75B | 制造商:Nanya Technology Corporation 功能描述:64M X 4 DDR DRAM, 0.75 ns, 66 Pin Plastic SMT |
| NT5DS64M4AT-7K | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|DDR|4X16MX4|CMOS|TSSOP|66PIN|PLASTIC |
| NT5DS64M4AT-8B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:256Mb Double Data Rate SDRAM |
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