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參數(shù)資料
| 型號： | NT5DS64M4AT |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 256Mb DDR333/300 SDRAM |
| 中文描述： | 256Mb的DDR333/300內(nèi)存 |
| 文件頁數(shù)： | 11/27頁 |
| 文件大?。?/td> | 269K |
| 代理商： | NT5DS64M4AT |
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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb DDR333/300 SDRAM
Preliminary
10/01
NANYA TECHNOLOGY CORP
. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Commands
Truth Tables 1a and 1b provide a reference of the commands supported by DDR SDRAM devices. A verbal description of each
commands follows.
Truth Table 1a: Commands
Name (Function)
CS
RAS
CAS
WE
Address
MNE
Notes
Deselect (Nop)
H
X
X
X
X
NOP
1, 9
No Operation (Nop)
L
H
H
H
X
NOP
1, 9
Active (Select Bank And Activate Row)
L
L
H
H
Bank/Row
ACT
1, 3
Read (Select Bank And Column, And Start Read Burst)
L
H
L
H
Bank/Col
Read
1, 4
Write (Select Bank And Column, And Start Write Burst)
L
H
L
L
Bank/Col
Write
1, 4
Burst Terminate
L
H
H
L
X
BST
1, 8
Precharge (Deactivate Row In Bank Or Banks)
L
L
H
L
Code
PRE
1, 5
Auto Refresh Or Self Refresh (Enter Self Refresh Mode)
L
L
L
H
X
AR / SR
1, 6, 7
Mode Register Set
L
L
L
L
Op-Code
MRS
1, 2
1. CKE is high for all commands shown except Self Refresh.
2. BA0, BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0 = 1, BA1 = 0 selects
Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A12 provide the op-code to be written to the selected Mode
Register.)
3. BA0-BA1 provide bank address and A0-A12 provide row address.
4. BA0, BA1 provide bank address; A0-A
i
provide column address (where
i
= 9 for x8 and 9, 11 for x4); A10 high enables the Auto Pre-
charge feature (nonpersistent), A10 low disables the Auto Precharge feature.
5. A10 LOW: BA0, BA1 determine which bank is precharged.
A10 HIGH: all banks are precharged and BA0, BA1 are “Don’t Care.”
6. This command is auto refreshif CKE is high; Self Refresh if CKE is low.
7. Internal refresh counter controls row and bank addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. Applies only to read bursts with Auto Precharge disabled; this command is undefined (and should not be used) for read bursts with Auto
Precharge enabled or for write bursts
9. Deselect and NOP are functionally interchangeable.
Truth Table 1b: DM Operation
Name (Function)
DM
DQs
Notes
Write Enable
L
Valid
1
Write Inhibit
H
X
1
1. Used to mask write data; provided coincident with the corresponding data.
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PDF描述 |
|---|---|
| NT5DS64M4AT-6 | 256Mb DDR333/300 SDRAM |
| NT5DS64M4AT-66 | 256Mb DDR333/300 SDRAM |
| NT5DS64M4AW | 256Mb DDR333/300 SDRAM |
| NT5DS64M4AW-6 | 256Mb DDR333/300 SDRAM |
| NT5DS64M4AW-66 | 256Mb DDR333/300 SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NT5DS64M4AT-6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:256Mb DDR333/300 SDRAM |
| NT5DS64M4AT-66 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:256Mb DDR333/300 SDRAM |
| NT5DS64M4AT-75B | 制造商:Nanya Technology Corporation 功能描述:64M X 4 DDR DRAM, 0.75 ns, 66 Pin Plastic SMT |
| NT5DS64M4AT-7K | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|DDR|4X16MX4|CMOS|TSSOP|66PIN|PLASTIC |
| NT5DS64M4AT-8B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:256Mb Double Data Rate SDRAM |
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