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參數(shù)資料
| 型號： | NT5DS32M8AW-75B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 256Mb Double Data Rate SDRAM |
| 中文描述： | 256MB雙數(shù)據(jù)速率SDRAM |
| 文件頁數(shù)： | 30/78頁 |
| 文件大小： | 1534K |
| 代理商： | NT5DS32M8AW-75B |
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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
REV 1.1
12/2001
30
NANYA TECHNOLOGY CORP
. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Writes
Write bursts are initiated with a Write command, as shown in timing figure
Write Command
on page 31.
The starting column and bank addresses are provided with the Write command, and Auto Precharge is either enabled or dis-
abled for that access. If Auto Precharge is enabled, the row being accessed is precharged at the completion of the burst. For
the generic Write commands used in the following illustrations, Auto Precharge is disabled.
During Write bursts, the first valid data-in element is registered on the first rising edge of DQS following the write command, and
subsequent data elements are registered on successive edges of DQS. The Low state on DQS between the Write command
and the first rising edge is known as the write preamble; the Low state on DQS following the last data-in element is known as
the write postamble. The time between the Write command and the first corresponding rising edge of DQS (t
DQSS
) is specified
with a relatively wide range (from 75% to 125% of one clock cycle), so most of the Write diagrams that follow are drawn for the
two extreme cases (i.e. t
DQSS
(min) and t
DQSS
(max)). Timing figure
Write Burst (Burst Length = 4)
on page 32 shows the two
extremes of t
DQSS
for a burst of four. Upon completion of a burst, assuming no other commands have been initiated, the DQs
and DQS enters High-Z and any additional input data is ignored.
Data for any Write burst may be concatenated with or truncated with a subsequent Write command. In either case, a continuous
flow of input data can be maintained. The new Write command can be issued on any positive edge of clock following the previ-
ous Write command. The first data element from the new burst is applied after either the last element of a completed burst or
the last desired data element of a longer burst which is being truncated. The new Write command should be issued x cycles
after the first Write command, where x equals the number of desired data element pairs (pairs are required by the 2n prefetch
architecture). Timing figure
Write to Write (Burst Length = 4)
on page 33 shows concatenated bursts of 4. An example of non-
consecutive Writes is shown in timing figure
Write to Write: Max DQSS, Non-Consecutive (Burst Length = 4)
on page 34. Full-
speed random write accesses within a page or pages can be performed as shown in timing figure
Random Write Cycles (Burst
Length = 2, 4 or 8)
on page 35. Data for any Write burst may be followed by a subsequent Read command. To follow a Write
without truncating the write burst, t
WTR
(Write to Read) should be met as shown in timing figure
Write to Read: Non-Interrupting
(CAS Latency = 2; Burst Length = 4)
on page 36.
Data for any Write burst may be truncated by a subsequent (interrupting) Read command. This is illustrated in timing figures
“Write to Read: Interrupting (CAS Latency =2; Burst Length = 8)”, “Write to Read: Minimum D
QSS
, Odd Number of Data (3 bit
Write), Interrupting (CAS Latency = 2; Burst Length = 8)”, and “Write to Read: Nominal D
QSS
, Interrupting (CAS Latency = 2;
Burst Length = 8)”. Note that only the data-in pairs that are registered prior to the t
WTR
period are written to the internal array,
and any subsequent data-in must be masked with DM, as shown in the diagrams noted previously.
Data for any Write burst may be followed by a subsequent Precharge command. To follow a Write without truncating the write
burst, t
WR
should be met as shown in timing figure
Write to Precharge: Non-Interrupting (Burst Length = 4)
on page 40.
Data for any Write burst may be truncated by a subsequent Precharge command, as shown in timing figures
Write to Pre-
charge: Interrupting (Burst Length = 4 or 8)
on page 41 to
Write to Precharge: Nominal DQSS (2 bit Write), Interrupting (Burst
Length = 4 or 8)
on page 43. Note that only the data-in pairs that are registered prior to the t
WR
period are written to the internal
array, and any subsequent data in should be masked with DM. Following the Precharge command, a subsequent command to
the same bank cannot be issued until t
RP
is met.
In the case of a Write burst being executed to completion, a Precharge command issued at the optimum time (as described
above) provides the same operation that would result from the same burst with Auto Precharge. The disadvantage of the Pre-
charge command is that it requires that the command and address busses be available at the appropriate time to issue the com-
mand. The advantage of the Precharge command is that it can be used to truncate bursts.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| NT5DS32M8AW-7K | 256Mb Double Data Rate SDRAM |
| NT5DS32M8AW-8B | 256Mb Double Data Rate SDRAM |
| NT5DS64M4AW-75B | 256Mb Double Data Rate SDRAM |
| NT5DS64M4AW-7K | 256Mb Double Data Rate SDRAM |
| NT5DS64M4AW-8B | 256Mb Double Data Rate SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NT5DS32M8AW-7K | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:256Mb Double Data Rate SDRAM |
| NT5DS32M8AW-8B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:256Mb Double Data Rate SDRAM |
| NT5DS32M8CS | 制造商:NANOAMP 制造商全稱:NANOAMP 功能描述:256Mb DDR Synchronous DRAM |
| NT5DS32M8CS-5T | 制造商:NANOAMP 制造商全稱:NANOAMP 功能描述:256Mb DDR Synchronous DRAM |
| NT5DS32M8CS-6K | 制造商:NANOAMP 制造商全稱:NANOAMP 功能描述:256Mb DDR Synchronous DRAM |
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