參數(shù)資料
型號(hào)： NT256D64S8HA0G-6
廠商： Electronic Theatre Controls, Inc.
英文描述： 184pin Two Bank Unbuffered DDR SDRAM MODULE
中文描述： 184pin兩個(gè)銀行無(wú)緩沖DDR SDRAM內(nèi)存模塊
文件頁(yè)數(shù)： 9/13頁(yè)
文件大?。?/td> 195K
代理商： NT256D64S8HA0G-6
NT256D64S8HA0G-6
256MB : 32M x 64
PC2700 Unbuffered DIMM
AC Timing Specifications for DDR SDRAM Devices Used on Module
( T
A
= 0 °C ~ 70 °C ; V
DDQ
= 2.5V ± 0.2V; V
DD
= 2.5V ± 0.2V, See AC Characteristics)
Preliminary,
11/2001
9
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
-6
Symbol
Parameter
Min.
-0.7
-0.7
0.45
0.45
6
7.5
0.45
0.45
1.75
-0.7
-0.7
Max.
+0.7
+0.7
0.55
0.55
12
12
+0.7
+0.7
0.4
Unit
Notes
t
AC
t
DQSCK
t
CH
t
CL
DQ output access time from CK/
CK
DQS output access time from CK/
CK
CK high-level width
CK low-level width
ns
ns
t
CK
t
CK
ns
ns
ns
ns
ns
ns
ns
ns
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4,15,16
1,2,3,4,15,16
1,2,3,4
1, 2, 3,4, 5
1, 2, 3,4, 5
1,2,3,4
CL=2.5
CL=2
t
CK
Clock cycle time
t
DH
t
DS
t
DIPW
t
HZ
t
LZ
t
DQSQ
DQ and DM input hold time
DQ and DM input setup time
DQ and DM input pulse width (each input)
Data-out high-impedance time from CK/
CK
Data-out low-impedance time from CK/
CK
DQS-DQ skew (DQS & associated DQ signals)
Minimum half CLK period for any given cycle;
defined by CLK high(t
CH
) or CLK low (t
CL
) time
Data output hold time from DQS
Write command to 1st DQS latching transition
DQS input low (high) pulse width
(write cycle)
DQS falling edge to CK setup time (write cycle)
DQS falling edge hold time from CK (write cycle)
Mode register set command cycle time
Write preamble setup time
Write postamble
Write preamble
Address and control input hold time (fast slew rate)
Address and control input setup time (fast slew rate)
Address and control input hold time (slow slew rate)
Address and control input setup time (slow slewrate)
Input pulse width
Read preamble
Read postamble
Active to Precharge command
Active to Active/Auto-refresh command period
Auto-refresh to Active/Auto-refresh command period
Active to Read or Write delay
Active to Read Command with Autoprecharge
Precharge command period
Active bank A to Active bank B command
Write recovery time
t
HP
t
CH
or t
CL
t
CK
1,2,3,4
t
QH
t
DQSS
t
HP
- 0.75ns
0.75
t
CK
t
CK
1,2,3,4
1,2,3,4
1.25
t
DQSL,H
0.35
t
CK
1,2,3,4
t
DSS
t
DSH
t
MRD
t
WPRES
t
WPST
t
WPRE
t
IH
t
IS
t
IH
t
IS
t
IPW
t
RPRE
t
RPST
t
RAS
t
RC
t
RFC
t
RCD
t
RAP
t
RP
t
RRD
t
WR
0.2
0.2
2
0
0.40
0.25
0.75
0.75
0.8
0.8
2.2
0.9
0.40
42
60
72
18
18
18
12
15
t
CK
t
CK
t
CK
ns
t
CK
t
CK
ns
ns
ns
ns
ns
t
CK
t
CK
ns
ns
ns
ns
ns
ns
ns
ns
1,2,3,4
1,2,3,4
1,2,3,4
1, 2, 3,4, 7
1, 2, 3,4, 6
1,2,3,4
2, 3, 4,9, 11,12
2, 3, 4,9, 11,12
2, 3, 4,10, 11,12, 14
2, 3, 4,10, 11,12, 14
2, 3, 4,12
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
0.60
1.1
0.60
120,000
t
DAL
Auto precharge write recovery + precharge time
(t
WR
/t
CK
)
+
(t
RP
/t
CK
)
1
75
200
t
CK
1, 2, 3,4, 13
t
WTR
t
XSNR
t
XSRD
t
REFI
Internal write to read command delay
Exit self-refresh to non-read command
Exit self-refresh to read command
Average Periodic Refresh Interval
t
CK
ns
t
CK
μs
1,2,3,4
1,2,3,4
1,2,3,4
1, 2, 3,4, 8
15.6
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參數(shù)描述
NT256D64S8HA0G-75B 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:184pin Two Bank Unbuffered DDR SDRAM MODULE
NT256D64S8HA0G-7K 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:184pin Two Bank Unbuffered DDR SDRAM MODULE
NT256D64S8HA0G-8B 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:184pin Two Bank Unbuffered DDR SDRAM MODULE
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