參數(shù)資料
型號: NT128D64S88A0G-8B
廠商: Electronic Theatre Controls, Inc.
英文描述: 184pin One Bank Unbuffered DDR SDRAM MODULE
中文描述: 一位銀行無緩沖184pin DDR SDRAM內(nèi)存模塊
文件頁數(shù): 8/15頁
文件大?。?/td> 191K
代理商: NT128D64S88A0G-8B
NT128D64S88A0G
128MB : 16M x 64
PC2100 / PC1600 Unbuffered DIMM
DC Electrical Characteristics and Operating Conditions
( TA = 0 °C ~ 70 °C ; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics)
Symbol
Parameter
V
DD
Supply Voltage
V
DDQ
I/O Supply Voltage
REV1.0
/
June 2001
8
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Min
Max
Units
Notes
2.3
2.7
V
1
2.3
2.7
V
1
V
SS
, V
SSQ
Supply Voltage, I/O Supply Voltage
0
0
V
V
REF
I/O Reference Voltage
0.49 x
V
DDQ
0.51 x
V
DDQ
V
1,2
V
TT
I/O Termination Voltage (System)
V
REF
– 0.04 V
REF
+ 0.04
V
1,3
V
IH(DC)
Input High (Logic1) Voltage
V
REF
+ 0.15
V
DDQ
+ 0.3
V
1
V
IL(DC)
Input Low (Logic0) Voltage
-0.3
V
REF
- 0.15
V
1
V
IN(DC)
Input Voltage Level, CK and
CK
Inputs
-0.3
V
DDQ
+ 0.3
V
1
V
ID(DC)
Input Differential Voltage, CK and
CK
Inputs
0.30
V
DDQ
+ 0.6
V
1,4
Address and
control inputs
-40
40
DQ0-63;
DQS0-7, 9-16
-5
5
I
I
Input Leakage Current
Any input 0V < = V
IN
< = V
DD
(All other pins not under test = 0V)
CK0,
CK0
CK1,
CK1
CK2,
CK2
-15
15
uA
1
DQ0-63;
DQS0-7, 9-16
-5
5
uA
1
I
OZ
Output Leakage Current
(DQs are disabled; 0V < = V
out
< = V
DDQ
SDA
-1
1
I
OH
Output High Current
(V
OUT =
V
DDQ
-0.373V, min V
REF
, min V
TT
)
-16.8
-
mA
1
I
OL
Output Low Current
(V
OUT
= 0.373, max V
REF
, max V
TT
)
16.8
-
mA
1
1. Inputs are not recognized as valid until V
REF
stabilizes.
2. V
REF
is expected to be equal to 0.5 V
DDQ
of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak
noise on V
REF
may not exceed 2% of the DC value.
3. V
TT
is not applied directly to the DIMM. V
TT
is a system supply for signal termination resistors, is expected to be set equal to V
REF
,
and must track variations in the DC level of V
REF
.
4. V
ID
is the magnitude of the difference between the input level on CK and the input level on
CK
.
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