參數(shù)資料
型號(hào)： NT128D64S88A0G-8B
廠商： Electronic Theatre Controls, Inc.
英文描述： 184pin One Bank Unbuffered DDR SDRAM MODULE
中文描述： 一位銀行無緩沖184pin DDR SDRAM內(nèi)存模塊
文件頁(yè)數(shù)： 10/15頁(yè)
文件大小： 191K
代理商： NT128D64S88A0G-8B
NT128D64S88A0G
128MB : 16M x 64
PC2100 / PC1600 Unbuffered DIMM
Operating, Standby, and Refresh Currents
REV1.0
/
June 2001
10
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
( TA = 0 °C ~ 70 °C ; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics)
Symbol
Parameter/Condition
PC1600
PC2100
Unit
Notes
I
DD0
Operating Curren
t: one bank; active / precharge; t
RC
=t
RC (MIN)
;
t
CK
= t
CK (MIN)
; DQ, DM, and DQS inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle
Operating Curren
t: one bank; active / read / precharge; Burst = 2;
t
RC
= t
RC (MIN)
; CL = 2.5; t
CK
= t
CK (MIN)
;I
OUT
= 0mA;
address and control inputs changing once per clock cycle
Precharge Power-Down Standby Curren
t:
all banks idle; power-down mode; CKE <= V
IL (MAX)
; t
CK
= t
CK (MIN)
Idle Standby Current:
CS >= V
IH (MIN)
; all banks idle; CKE >= V
IH(MIN)
;
t
CK
= t
CK (MIN)
; address and control inputs changing once per clock cycle
Active Power-Down Standby Curren
t: one bank active;
power-down mode; CKE <= V
IL (MAX)
; t
CK
= t
CK (MIN)
Active Standby Curren
t: one bank; active / precharge; CS >= V
IH (MIN)
;
CKE >= V
IH (MIN)
; t
RC
= t
RAS (MAX)
; t
CK
= t
CK (MIN)
; DQ, DM, and DQS
inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle
Operating Current:
one bank; Burst = 2; reads; continuous burst;
address and control inputs changing once per clock cycle;
DQ and DQS outputs changing twice per clock cycle; CL = 2.5;
t
CK
= t
CK (MIN)
; I
OUT
= 0mA
Operating Curren
t: one bank; Burst = 2; writes; continuous burst;
address and control inputs changing once per clock cycle;
DQ and DQS inputs changing twice per clock cycle; CL=2.5;
t
CK
= t
CK (MIN)
600
680
mA
1,2
I
DD1
720
880
mA
1,2
I
DD2P
120
120
mA
1,2
I
DD2N
240
280
mA
1,2
I
DD3P
120
120
mA
1,2
I
DD3N
400
480
mA
1,2
I
DD4R
1040
1320
mA
1,2
I
DD4W
920
1200
mA
1,2
t
RC
= t
RFC (MIN)
t
RC
= 15.625 μs
1280
126
16
1360
126
16
mA
mA
mA
1,2
1,2,4
1,2,3
I
DD5
Auto-Refresh Curren
t:
I
DD6
1. I
DD
specifications are tested after the device is properly initialized.
2. Input slew rate = 1V/ ns .
3. Enables on-chip refresh and address counters.
4. Current at 15.625 μs is time averaged value of I
DD5
at t
RFC MIN
and I
DD2P
over 15.625 μs.
Self-Refresh Curren
t: CKE <= .2V
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