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參數(shù)資料
| 型號： | NSBMC016 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Burst Memory Controller(脈沖存儲控制器) |
| 中文描述： | 突發(fā)內(nèi)存控制器（脈沖存儲控制器） |
| 文件頁數(shù)： | 7/18頁 |
| 文件大?。?/td> | 266K |
| 代理商： | NSBMC016 |
Functional Description
(Continued)
BLOCK ADDRESS FIELD
Once configured, a NSBMC096 responds to access re-
quests within the programmed block address range. The
programmed value sets the starting address of the block,
while the size of the block is determined by the DRAM size
control bits. The block address, however, is constrained to
start on a boundary that is an integer multiple of the block
size. For example, if 1 Mbit
c
1 DRAMs are used, the mem-
ory block size is 8 Mbytes and must start on an 8 Mbyte
boundary.
TL/V/11805–6
FIGURE 3. Configuration Register Control Fields
CYCLE EXTEND
In order to maximize the choice of memory device speeds
that may be used for various system clock rates, the Row
Address Strobe (RAS) period for a basic access may be
programmed for either 3 or 4 clock cycles. When cleared to
‘‘0’’, configuration bit 20 indicates that 3 clock cycles (2 wait
states) are to be used (2-0-0-0 burst access), when set to
‘‘1’’, 4 are required (3 wait states for a basic access 3-0-1-0
for burst). Setting bit 20 to ‘‘1’’ also has the effect of in-
creasing the RAS pre-charge time by 1 clock cycle. Calcula-
tion of the number of cycles required per access type is
detailed in the NSBMC096 Application Guide.
BURST WRITE DISABLE
It bit 19 of the configuration word is set to ‘‘1’’, burst write
cycles are disabled. Subsequently, when the NSBMC096
detects the start of a burst write access, it asserts the
BTERM signal to request that the processor terminate the
burst in progress and transfer the remaining data using a
series of simple cycles. This feature is included in order to
facilitate the implementation of systems without latching
buffers. Latching buffers are required to prevent data hold
violations during burst writes. If burst writes are disabled,
latching buffers are no longer required.
ROW ADDRESS HOLD
Bit 18 of the configuration register controls the time at which
the memory address switches from row to column address.
This allows the designer to control the address hold time
relative to RAS so that the slowest memory can be used for
a range of clock speeds. Setting Bit 18 yields the maximum
row address hold time, clearing it shortens the row address
hold in favor of additional column address setup.
INTERLEAVE DISABLE
In cost sensitive applications, it is sometimes desirable for a
system to operate with a single bank of memory so as to
reduce the minimum memory required. In this case the inter-
leave mode bit is programmed to ‘‘1’’. If a second bank of
memory is added, this bit can be programmed to ‘‘0’’ to
enable interleave operation and peak performance. In non-
interleave mode a burst access is either 2-1-1-1 with Cycle
Extend disabled, or 3-2-2-2 with Extended Cycle. Non-inter-
leave operation uses only leaf A signals.
7
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| NSBMC025 | Burst Memory Controller(脈沖存儲控制器) |
| NSBMC096 | Burst Memory Controller(脈沖存儲控制器) |
| NSBMC033 | Burst Memory Controller(脈沖存儲控制器) |
| NSBMC096VF | NSBMC096-16/-25/-33 Burst Memory Controller |
| NSBMC096-16 | NSBMC096-16/-25/-33 Burst Memory Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NSBMC096 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| NSBMC096-16 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:NSBMC096-16/-25/-33 Burst Memory Controller |
| NSBMC096VF | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:NSBMC096-16/-25/-33 Burst Memory Controller |
| NSBMC096VF-16 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller |
| NSBMC096VF-25 | 功能描述:IC CONTROLLER BURST MEM 132-PQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 - 控制器 系列:- 標準包裝:45 系列:- 控制器類型:靜態(tài) RAM（SRAM） 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:16-SOIC W 包裝:管件 |
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