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參數(shù)資料
| 型號(hào)： | NS32FX211V |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | Microprocessor Compatible Real Time C |
| 中文描述： | 0 TIMER(S), REAL TIME CLOCK, PQCC20 |
| 封裝： | PLASTIC, LCC-20 |
| 文件頁數(shù)： | 4/12頁 |
| 文件大?。?/td> | 171K |
| 代理商： | NS32FX211V |
Switching Time Waveforms
Read Cycle Timing (Notes 5 and 7)
TL/F/11011–3
Write Cycle Timing (Notes 5 and 6)
TL/F/11011–4
FIGURE 2
Functional Description
The NS32FX211 is a bus oriented microprocessor real time
clock.
Crystal Oscillator
This consists of a CMOS inverter/amplifier with an on-chip
bias resistor. Externally a 22 pF capacitor, a 6 pF–40 pF
trimmer capacitor and a crystal are suggested to complete
the 32.768 kHz timekeeping oscillator circuit.
The 6 pF–40 pF trimmer fine tunes the crystal load imped-
ance, optimizing the oscillator stability. When properly ad-
justed (i.e., to the crystal frequency of 32.768 kHz), the cir-
cuit will display a frequency variation with voltage of less
than 3 ppm/V. When an external oscillator is used, connect
to oscillator input and float (no connection) the oscillator
output.
When the chip is enabled into test mode, the oscillator is
gated onto the interrupt output pin giving a buffered oscilla-
tor output that can be used to set the crystal frequency
when the device is installed in a system.
Divider Chain
The crystal oscillator is divided down in three stages to pro-
duce a 10 Hz frequency setting pulse. The first stage is a
non-integer divider which reduces the 32.768 kHz input to
20.720 kHz. This is further divided by a 9-stage binary ripple
counter giving an output frequency of 60 Hz. A 3-stage
Johnson counter divides this by six, generating a 10 Hz out-
put. The 10 Hz clock is gated with the 32.768 kHz crystal
frequency to provide clock setting pulses of 15.26
m
s dura-
tion. The setting pulse drives all the time registers on the
device which are synchronously clocked by this signal. All
time data and data-changed flag change on the falling edge
of the clock setting pulse.
Data-Changed Flag
The data-changed flag is set by the clock setting pulse to
indicate that the time data has been altered since the clock
was last read. This flag occupies bit 3 of the control register
where it can be tested by the processor to sense data-
changed. It will be reset by a read of the control register.
See the section, ‘‘Methods of Device Operation’’, for sug-
gested clock reading techniques using this flag.
Seconds Counters
There are three counters for seconds:
a. tenths of seconds
b. units of seconds
c. tens of seconds
The registers are accessed at the addresses shown in Ta-
ble I. The tenths of seconds register is reset to 0 when the
clock start/stop bit (bit 2 of the control register) is set to
4
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