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參數(shù)資料
| 型號(hào)： | NS32FX211V |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類(lèi)： | XO, clock |
| 英文描述： | Microprocessor Compatible Real Time C |
| 中文描述： | 0 TIMER(S), REAL TIME CLOCK, PQCC20 |
| 封裝： | PLASTIC, LCC-20 |
| 文件頁(yè)數(shù)： | 3/12頁(yè) |
| 文件大小： | 171K |
| 代理商： | NS32FX211V |
AC Switching Characteristics
READ TIMING: DATA FROM PERIPHERAL TO MICROPROCESSOR
V
DD
e
5V
g
5%, C
L
e
100 pF
Symbol
Parameter
Commercial Specification
Units
T
A
e
0
§
C to
a
75
§
C
Min
Typ
Max
t
AD
Address Bus Valid to Data Valid
390
650
ns
t
CSD
Chip Select On to Data Valid
140
300
ns
t
RD
Read Strobe On to Data Valid
140
300
ns
t
RW
Read Strobe Width (Note 3, Note 7)
300
DC
ns
t
RA
Address Bus Hold Time from Trailing
Edge of Read Strobe
0
ns
t
CSH
Chip Select Hold Time from Trailing
Edge of Read Strobe
0
ns
t
RH
Data Hold Time from Trailing
Edge of Read Strobe
70
160
ns
t
HZ
Time from Trailing Edge of Read Strobe
Unitl O/P Drivers are TRI-STATE
é
250
ns
WRITE TIMING: DATA FROM MICROPROCESSOR TO PERIPHERAL
V
DD
e
5V
g
5%
Symbol
Parameter
Commercial Specification
Units
T
A
e
0
§
C to
a
70
§
C
Min
Typ
Max
t
AW
Address Bus Valid to Write Strobe
O
(Note 4, Note 6)
400
125
ns
t
CSW
Chip Select On to Write Strobe
O
Data Bus Valid to Write Strobe
O
250
100
ns
t
DW
400
220
ns
t
WW
Write Strobe Width (Note 6)
250
95
ns
t
WCS
Chip Select Hold Time Following
Write Strobe
O
0
ns
t
WA
Address Bus Hold Time Following
Write Strobe
O
0
ns
t
WD
Data Bus Hold Time Following
Write Strobe
O
100
35
ns
t
AWS
Address Bus Valid before
Start or Write Strobe
70
20
ns
Note 3:
Except for special case restriction: with interrupts programmed, max read strobe width of control register (ADDR 0) is 30 ms. See section on Interrupt
Programming.
Note 4:
All timings measured to the trailing edge of write strobe (data latched by the trailing edge of WR).
Note 5:
Input test waveform peak voltages are 2.4V and 0.4V. Output signals are measured to their 2.4V and 0.4V levels.
Note 6:
Write stobe as used in the Write Timing Table is defined as the period when both chip select and write inputs are low, ie., WS,
e
CS
a
WR. Hence write
strobe commences when both signals are low, and terminates when the first signal returns high.
Note 7:
Read strobe as used in the Read Timing Table is defined as the period when both chip select and read inputs are low, ie., RS
e
CS
a
RD.
Note 8:
Typical numbers are at V
CC
e
5.0V and T
A
e
25
§
C.
3
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