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參數(shù)資料
| 型號(hào)： | NE5230D |
| 廠商： | ON Semiconductor |
| 文件頁(yè)數(shù)： | 16/18頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC OPAMP LOW VOLTAGE 8-SOIC |
| 標(biāo)準(zhǔn)包裝： | 98 |
| 放大器類(lèi)型： | 通用 |
| 電路數(shù)： | 1 |
| 輸出類(lèi)型： | 滿擺幅 |
| 轉(zhuǎn)換速率： | 0.25 V/µs |
| 增益帶寬積： | 600kHz |
| 電流 - 輸入偏壓： | 40nA |
| 電壓 - 輸入偏移： | 400µV |
| 電流 - 電源： | 1.1mA |
| 電流 - 輸出 / 通道： | 32mA |
| 電壓 - 電源，單路/雙路(±)： | 1.8 V ~ 15 V，±0.9 V ~ 7.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOICN |
| 包裝： | 管件 |
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NE5230, SA5230, SE5230
http://onsemi.com
7
Output Stage
Processing output voltage swings that nominally reach to
less than 100 mV of either supply voltage can only be
achieved by a pair of complementary commonemitter
connected transistors. Normally, such a configuration
causes complex feedforward signal paths that develop by
combining biasing and driving which can be found in
previous low supply voltage designs. The unique output
stage of the NE5230 separates the functions of driving and
biasing, as shown in the simplified schematic of Figure 2 and
has the advantage of a shorter signal path which leads to
increasing the effective bandwidth.
This output stage consists of two parts: the Darlington
output transistors and the class AB control regulator. The
output transistor Q3 connected with the Darlington
transistors Q4 and Q5 can source up to 10 mA to an output
load. The output of NPN Darlington connected transistors
Q1 and Q2 together are able to sink an output current of
10 mA. Accurate and efficient class AB control is necessary
to insure that none of the output transistors are ever
completely cut off. This is accomplished by the differential
amplifier (formed by Q8 and Q9) which controls the biasing
of the output transistors. The differential amplifier compares
the summed voltages across two diodes, D1 and D2, at the
base of Q8 with the summed voltages across the
baseemitter diodes of the output transistors Q1 and Q3. The
baseemitter voltage of Q3 is converted into a current by Q6
and R6 and reconverted into a voltage across the
baseemitter diode of Q7 and R7. The summed voltage
across the baseemitter diodes of the output transistors Q3
and Q1 is proportional to the logarithm of the product of the
push and pull currents IOP and ION, respectively. The
combined voltages across diodes D1 and D2 are
proportional to the logarithm of the square of the reference
current IB1. When the diode characteristics and
temperatures of the pairs Q1, D1 and Q3, Q2 are equal, the
relation IOP × ION IB1 × IB1 is satisfied.
Separating the functions of biasing and driving prevents
the driving signals from becoming delayed by the biasing
circuit. The output Darlington transistors are directly
accessible for inphase driving signals on the bases of Q5
and Q2. This is very important for simple highfrequency
compensation. The output transistors can be highfrequency
compensated by Miller capacitors CM1A and CM1B
connected from the collectors to the bases of the output
Darlington transistors.
A generalpurpose op amp of this type must have enough
openloop gain for applications when the output is driving
a low resistance load. The NE5230 accomplishes this by
inserting an intermediate commonemitter stage between
the input and output stages. The three stages provide a very
large gain, but the op amp now has three natural dominant
poles one at the output of each commonemitter stage.
Frequency compensation is implemented with a simple
scheme of nested, polesplitting Miller integrators. The
Miller capacitors CM1A and CM1B are the first part of the
nested structure, and provide compensation for the output
and intermediate stages. A second pair of Miller integrators
provide polesplitting compensation for the pole from the
input stage and the pole resulting from the compensated
combination of poles from the intermediate and output
stages. The result is a stable, internallycompensated op
amp with a phase margin of 70
°.
Q5
Ib1
Ib2
Ib3
Ib5
Ib4
Q4
Q6
Q8
Q9
D1
Q7
Q3
D2
Q1
Q2
R7
R6
CM1B
CM1A
Vb2
Vb5
VCC
VEE
VOUT
IOP
ION
Figure 2. Output Stage
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參數(shù)描述 |
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| NE5230DG | 功能描述:運(yùn)算放大器 - 運(yùn)放 1.8V Single Rail to Rail Commercial Temp RoHS:否 制造商:STMicroelectronics 通道數(shù)量:4 共模抑制比（最小值）:63 dB 輸入補(bǔ)償電壓:1 mV 輸入偏流（最大值）:10 pA 工作電源電壓:2.7 V to 5.5 V 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-16 轉(zhuǎn)換速度:0.89 V/us 關(guān)閉:No 輸出電流:55 mA 最大工作溫度:+ 125 C 封裝:Reel |
| NE5230DR2 | 功能描述:運(yùn)算放大器 - 運(yùn)放 1.8V Single Rail to RoHS:否 制造商:STMicroelectronics 通道數(shù)量:4 共模抑制比（最小值）:63 dB 輸入補(bǔ)償電壓:1 mV 輸入偏流（最大值）:10 pA 工作電源電壓:2.7 V to 5.5 V 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-16 轉(zhuǎn)換速度:0.89 V/us 關(guān)閉:No 輸出電流:55 mA 最大工作溫度:+ 125 C 封裝:Reel |
| NE5230DR2G | 功能描述:運(yùn)算放大器 - 運(yùn)放 1.8V Single Rail to Rail Commercial Temp RoHS:否 制造商:STMicroelectronics 通道數(shù)量:4 共模抑制比（最小值）:63 dB 輸入補(bǔ)償電壓:1 mV 輸入偏流（最大值）:10 pA 工作電源電壓:2.7 V to 5.5 V 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-16 轉(zhuǎn)換速度:0.89 V/us 關(guān)閉:No 輸出電流:55 mA 最大工作溫度:+ 125 C 封裝:Reel |
| NE5230N | 功能描述:運(yùn)算放大器 - 運(yùn)放 1.8V Single Rail to RoHS:否 制造商:STMicroelectronics 通道數(shù)量:4 共模抑制比（最小值）:63 dB 輸入補(bǔ)償電壓:1 mV 輸入偏流（最大值）:10 pA 工作電源電壓:2.7 V to 5.5 V 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-16 轉(zhuǎn)換速度:0.89 V/us 關(guān)閉:No 輸出電流:55 mA 最大工作溫度:+ 125 C 封裝:Reel |
| NE5230NG | 功能描述:運(yùn)算放大器 - 運(yùn)放 1.8V Single Rail to Rail Commercial Temp RoHS:否 制造商:STMicroelectronics 通道數(shù)量:4 共模抑制比（最小值）:63 dB 輸入補(bǔ)償電壓:1 mV 輸入偏流（最大值）:10 pA 工作電源電壓:2.7 V to 5.5 V 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-16 轉(zhuǎn)換速度:0.89 V/us 關(guān)閉:No 輸出電流:55 mA 最大工作溫度:+ 125 C 封裝:Reel |
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