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參數(shù)資料
| 型號(hào)： | NDP710B |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | JFETs |
| 英文描述： | N-Channel Enhancement Mode Field Effect Transistor |
| 中文描述： | 40 A, 100 V, 0.042 ohm, N-CHANNEL, Si, POWER, MOSFET, TO-220AB |
| 封裝： | TO-220, 3 PIN |
| 文件頁(yè)數(shù)： | 1/6頁(yè) |
| 文件大?。?/td> | 74K |
| 代理商： | NDP710B |
May 1994
NDP710A / NDP710AE / NDP710B / NDP710BE
NDB710A / NDB710AE / NDB710B / NDB710BE
N-Channel Enhancement Mode Field Effect Transistor
General Description
These N-channel enhancement mode power field
effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This
very high density process has been especially
tailored to minimize on-state resistance, provide
superior switching performance, and withstand high
energy pulses in the avalanche and commutation
modes. These devices are particularly suited for low
voltage applications such as automotive, DC/DC
converters, PWM motor controls, and other battery
powered circuits where fast switching, low in-line
power loss, and resistance to transients are needed.
Features
_____________________________________________________________________
Absolute Maximum Ratings
T
C
= 25°C unless otherwise noted
NDP710A NDP710AE
NDB710A NDB710AE
Symbol Parameter
NDP710B NDP710BE
NDB710B NDB710BE
Units
V
DSS
V
DGR
V
GSS
Drain-Source Voltage
100
V
Drain-Gate Voltage (R
GS
< 1 M
)
Gate-Source Voltage - Continuous
100
V
±20
V
- Nonrepetitive (t
P
< 50
μ
s)
Drain Current - Continuous
±40
V
I
D
42
40
A
- Pulsed
168
160
A
P
D
Total Power Dissipation @ T
C
= 25
°
C
Derate above 25
°
C
150
W
1
W/
°
C
T
J
,T
STG
T
L
Operating and Storage Temperature Range
-65 to 175
°C
Maximum lead temperature for soldering
purposes, 1/8" from case for 5 seconds
275
°C
NDP710.SAM
42 and 40A, 100V. R
DS(ON)
= 0.038 and 0.042
.
Critical DC electrical parameters specified at
elevated temperature.
Rugged internal source-drain diode can eliminate
the need for an external Zener diode transient
suppressor.
175°C maximum junction temperature rating.
High density cell design (3 million/in2) for extremely
low R
DS(ON)
.
TO-220 and TO-263 (D
2
PAK) package for both
through hole and surface mount applications.
D
G
S
1997 Fairchild Semiconductor Corporation
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