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參數(shù)資料
| 型號(hào)： | ND12S0A0V50PNFA |
| 廠商： | Delta Electronics, Inc. |
| 英文描述： | Delphi ND Series Non-Isolated Point of Load DC/DC Power Modules: 12Vin, 0.9V~3.63Vout, 50Aout |
| 中文描述： | 德?tīng)柛ｂS系列非隔離負(fù)載點(diǎn)DC / DC電源模塊：12Vin，0.9?3.63Vout，50Aout |
| 文件頁(yè)數(shù)： | 9/12頁(yè) |
| 文件大?。?/td> | 515K |
| 代理商： | ND12S0A0V50PNFA |
DS_ND12S10A_03082007
9
FEATURES DESCRIPTIONS (CON.)
The output can also be set by an external voltage
connected to trim pin as shown in Figure 28
Figure 28:
output voltage trim with voltage source
To use voltage trim, the trim equation for the ND50 is
(please refer to Fig.28):
Vout is the desired output voltage
Vt is the external trim voltage
Rs is the resistance between Trim and Ground (in K
)
Rt is the resistor to be defined with the trim voltage (in K
)
Below is an example about using this voltage trim equation:
Example:
If Vt=1.25V, desired Vout=2.5V and Rs=1k
Power Good
The converter provides an open collector signal called
Power Good. This output pin uses positive logic and is
open collector. This power good output is ale to sink 5mA
and set high when the output is within
±10% of output set
point. The power good signal is pulled low when output is
not within ±10% of Vout or Enable is OFF.
Output Capacitance
There is output capacitor on the ND series modules.
Hence, an external output capacitor is required for stable
operation.
Voltage Margining Adjustment
Output voltage margin adjusting can be implemented in
the ND modules by connecting a resistor, R
margin-up
, from
the Trim pin to the Ground for margining
up the output
voltage. Also, the output voltage can be adjusted lower by
connecting a resistor, R
margin-down
, from the Trim pin to the
voltage source Vt. Figure 29 shows the circuit
configuration for output voltage margining adjustment.
Figure 29:
Circuit configuration for output voltage margining
Reflected Ripple Current and Output Ripple and
Noise Measurement
The measurement set-up outlined in Figure 30 has been
used for both input reflected/ terminal ripple current and
output voltage ripple and noise measurements on ND
series converters.
Cs=270
μ
F*1, Ltest=1.4uH, Cin=270
μ
F*2. Cout=680uF*4
Figure 30:
Input reflected ripple/ capacitor ripple current and
output voltage ripple and noise measurement setup for ND50
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