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參數(shù)資料
| 型號： | NCV7510DW |
| 廠商： | ON SEMICONDUCTOR |
| 英文描述： | FlexMOS Programmable Peak and Hold PWM MOSFET Predriver |
| 中文描述： | FlexMOS可編程峰值和保持MOSFET的預(yù)驅(qū)動器的PWM |
| 文件頁數(shù)： | 9/22頁 |
| 文件大小： | 160K |
| 代理商： | NCV7510DW |
NCV7510
http://onsemi.com
9
ELECTRICAL CHARACTERISTICS (continued)
(5 V < VDRN < 26 V, 4.75 V < V
DD
< 5.25 V, 40
°
C < T
J
< 125
°
C, unless
otherwise specified.) (Note 4
)
Characteristic
Conditions
Min
Typ
Max
Unit
Overcurrent Comparator
Input Bias Current
V
OCP
= 3.0 V
–
0.26
3.0
A
Linear Input Voltage Range
1.0
–
3.0
V
Mode Select Threshold
V
DD
= 5.0 V
4.2
4.5
4.8
V
Internal Overcurrent Reference
V
OCP
= V
DD
= 5.0 V
2.7
3.0
3.3
V
Detection Blanking Time
(See Figure 7)
Time to FAULT output low
1.25
2.5
5.0
s
Antisaturation Detect
GATE MOSFET
Auxiliary Register Bit 5 = 0, VDRNV
SRC
Auxiliary Register Bit 5 = 1, VDRNV
SRC
0.96
1.92
1.20
2.40
1.44
2.88
V
V
CLAMP MOSFET
Auxiliary Register Bit 4 = 0, V
SRC
V
PGND
Auxiliary Register Bit 4 = 1, V
SRC
V
PGND
0.2
0.4
0.4
0.8
0.6
1.2
V
V
SRC Input Bias Current
V
SRC
= 14 V, V
GATE
= 14 V
V
SRC
= 0 V, V
GATE
= 0 V
–
10
0.44
–
4.0
–
A
A
Detection Blanking Time
(See Figure 8)
Time to FAULT output low; GATE or CLAMP
5.0
10
20
s
Serial Peripheral Interface
(VDRN = 14 V, V
DD
= 5.0 V, C
so
= 200 pF) (Figure 9)
SCLK Clock Period
250
–
–
ns
Maximum Input Capacitance
Sl, SCLK; (Note 5)
–
–
12
pF
SCLK High Time
f
sclk
= 4.0 MHz, SCLK = 2.0 V to 2.0 V
125
–
–
ns
SCLK Low Time
f
sclk
= 4.0 MHz. SCLK = 0.8 V to 0.8 V
125
–
–
ns
Sl Setup Time
Sl =0.8 V/2.0 V to SCLK = 2.0 V
f
SCLK
= 4.0 MHz (Note 5)
25
–
–
ns
Sl Hold Time
SCLK =2.0 V to Sl = 0.8 V/2.0 V
f
SCLK
= 4.0 MHz (Note 5)
25
–
–
ns
SO Rise Time
(10% V
SO
to 90% V
DD
)
C
so
= 200 pF (Note 5)
–
25
50
ns
SO Fall Time
(90% V
SO
to 10% V
DD
)
C
so
= 200 pF (Note 5)
–
–
50
ns
CSB Setup Time
CSB = 0.8 V to SCLK = 2.0 V
(Note 5)
60
–
–
ns
CSB Hold Time
SCLK = 0.8 V to CSB = 2.0 V
(Note 5)
75
–
–
ns
SO Delay Time
SCLK =0.8 V to SO Data Valid
f
SCLK
= 4.0 MHz (Note 5)
–
65
125
ns
Transfer Delay Time
CSB rising edge to next falling edge.
(Note 5)
1.0
–
–
s
4. Designed to meet these characteristics over the stated voltage and temperature recommended operating ranges, though may not be 100%
parametrically tested in production.
5. Guaranteed by design.
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