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參數(shù)資料
| 型號： | NCV7510DW |
| 廠商： | ON SEMICONDUCTOR |
| 英文描述： | FlexMOS Programmable Peak and Hold PWM MOSFET Predriver |
| 中文描述： | FlexMOS可編程峰值和保持MOSFET的預(yù)驅(qū)動器的PWM |
| 文件頁數(shù)： | 19/22頁 |
| 文件大小： | 160K |
| 代理商： | NCV7510DW |
NCV7510
http://onsemi.com
19
DETAILED OPERATING DESCRIPTION (continued)
Operational Behavior
General
The NCV7510 is designed to maintain the programmed
load current at the PKHI and PKLO or at the HDHI and
HDLO reference values. While the device’s flexibility
allows all of these to be programmed to the same value, a
nonzero value is nonetheless required and the minimum
value is constrained by the NCV7510’s DC and AC
capabilities. It is also possible to reverse the order of the
PKHI|PKLO and HDHI|HDLO register values such that the
HI value is less than the LO value. While this is unlikely to
result in damage to the application, it will certainly lead to
bizarre behavior.
As previously noted, the PKHI program value may not be
reached during engine cranking when battery voltage may
initially dip to about 56 volts, particularly when driving
low resistance loads. This has additional implications for
both the external bootstrap circuitry (duty cycle
and openload detection behavior, both of which are
discussed in other sections of this data sheet.
The NCV7510’s ability to maintain the programmed load
currents is constrained by the
total
of the NCV7510’s
inherent DC accuracy and loop response delay, the load
characteristics, and any additional delays imposed by
external compensation circuitry, whether slewrate limiting
or other filtering designed to attenuate the egress or ingress
of radiated or conducted EMI.
100%)
Mode Control
The dwell timer selects which pair of the peak or hold
registers is setting the internal DAC and thus determines
whether the device is operating in the peak mode or the hold
mode. Bit D
3
of the AUX register determines whether a
logic level at the PCLK input directly controls the dwell time
or whether the internal dwell timer divides down an external
clock signal at the PCLK input.
When AUX D
3
=1, the control loop will be placed in the
peak mode when PCLK=0 and in the hold mode when
PCLK=1. When AUX D
3
=0, the control loop state will be
determined by the state of the dwell timer. The dwell time is
programmed via prescale divisor AUX register bits D
2
D
0
and by the 8bit DWELL timer register.
In the following sections, “dwell timer” means either the
state of the logic level at the PCLK input or the state of the
internal dwell timer.
Output Control
The state of the GATE and CLAMP outputs is determined
by the ENA and CONTROL inputs and by the state of the
control loop. In the absence of any faults, the state of the
control loop is determined by the contents of the peak and
hold registers, the state of the dwell timer, and the magnitude
of the load current.
The output control cycle begins when both the ENA and
CONTROL logic inputs are asserted high and ends when
either input is asserted low. At the beginning of each control
cycle the dwell timer and protection circuitry are initialized,
and the internal DAC is initialized to the PKHI register value
(if the dwell time register content is nonzero or if AUX
D
3
=1 and PCLK=0) or to the HDHI register value (if the
dwell time register content is null or if AUX D
3
=1 and
PCLK=1). The GATE and CLAMP output states will be
determined by the state of the control loop. At the end of
each control cycle the GATE and CLAMP outputs are driven
low, the dwell timer is reset, and open load fault data is
transferred into the SPI shift register if an open load fault
exists.
Control Loop
Load current is converted to a voltage via an external
sense resistor and compared with the programmed internal
DAC voltages. During the dwell time, the load current is
compared to the DAC voltages set by the peak high and peak
low register values. When the dwell time expires, the load
current is compared to the DAC voltages set by the hold high
and hold low register values. The state of the control loop is
reflected at the LOOP output such that a logic low indicates
that load current is less than the programmed DAC
reference.
When the load current is less than the peak or hold high
current, the GATE output is at the V
B
potential and the
CLAMP output is at PGND. When the load current is greater
than the peak or hold HI current, the DAC voltage is set to
the peak or hold LOW register value, the GATE output is
driven to PGND and the CLAMP output is driven to V
DD
.
When the load current is less than the peak or hold low
current, the DAC voltage is set to the peak or hold HIGH
register value, the GATE output is driven to V
B
and the
CLAMP output is driven to PGND.
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