參數(shù)資料
型號(hào): NCV7380DR2
廠商: ON SEMICONDUCTOR
元件分類: 通用總線功能
英文描述: LIN Transceiver
中文描述: LINE TRANSCEIVER, PDSO8
封裝: LEAD FREE, SOIC-8
文件頁(yè)數(shù): 5/14頁(yè)
文件大小: 92K
代理商: NCV7380DR2
NCV7380
http://onsemi.com
5
ELECTRICAL CHARACTERISTICS
(continued)
(V
S
= 6.0 to 18 V, V
CC
= 4.5 to 5.5 V and T
A
= 40 to 125
°
C unless otherwise noted.)
Characteristic
Symbol
Condition
Min
Typ
Max
Unit
TXD
High Level Input Voltage
V
ih
Rising Edge
0.7*V
CC
V
Low Level Input Voltage
V
il
Falling Edge
0.3*V
CC
V
TxD Pull Up Resistor
R
IH_TXD
V
TxD
= 0 V
10
15
20
k
RXD
Low Level Output Voltage
V
ol_rxd
I
RxD
= 2.0 mA
0.9
V
Leakage Current
V
leak_rxd
V
RxD
= 5.5 V, Recessive
1.0
1.0
A
AC CHARACTERISTICS
Propagation Delay Transmitter
(Notes 9 and 11)
t
trans_pdf
t
trans_pdr
Bus Loads: 1.0 K /1.0 nF,
660 /6.8 nF, 500 /10 nF
5.0
s
Propagation Delay Transmitter Symmetry
(Notes 7 and 11)
t
trans_sym
Calculate t
trans_pdf
t
trans_pdr
2.0
2.0
s
Propagation Delay Receiver
(Notes 7, 8, 9, 11 and 14)
t
rec_pdf
t
rec_pdr
C
RxD
= 20 pF
6.0
s
Propagation Delay Receiver Symmetry
(Notes 7 and 8)
t
rec_sym
Calculate t
trans_pdf
t
trans_pdr
1.5
1.5
s
Slew Rate Rising and Falling Edge,
High Battery (Notes 7 and 12)
t
SR_HB
Bus Loads: V
S
= 18 V,
1.0 K /1.0 nF, 660 /6.8 nF,
500 /10 nF
1.0
2.0
3.0
V/ s
Slew Rate Rising and Falling Edge,
Low Battery (Notes 7 and 12)
t
SR_LB
Bus Loads: V
S
= 7.0 V,
1.0 K /1.0 nF, 660 /6.8 nF,
500 /10 nF
0.5
2.0
3.0
V/ s
Slope Symmetry, High Battery
(Notes 7 and 12)
t
ssym_HB
Bus Loads: V
S
= 18 V,
1.0 K /1.0 nF, 660 /6.8 nF,
500 /10 nF, Calculate
t
sdom
t
srec
5.0
5.0
s
Bus Duty Cycle (Notes 8 and 15)
D1
D2
Calculate t
BUS_rec(min)
/100 s
Calculate t
BUS_rec(max)
/100 s
0.396
0.581
s/ s
s/ s
Receiver Debounce Time
(Notes 10, 13 and 14)
t
rec_deb
BUS Rising and Falling Edge
1.5
4.0
s
7. In accordance to LIN physical layer specification 1.3.
8. In accordance to LIN physical layer specification 2.0.
9. Propagation delays are not relevant for LIN protocol transmission, only symmetry.
10.No production test, guaranteed by design and qualification.
11.See Figure 2 Input/Output Timing.
12.See Figure 7 Slope Time Calculation.
13.See Figure 3 Receiver Debouncing.
14.This parameter is tested by applying a square wave to the bus. The minimum slew rate for the bus rising and falling edges is 50 V/ s.
15.See Figure 8 Duty Cycle Measurement and Calculation.
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