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參數(shù)資料
| 型號： | NCV7380DR2 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 通用總線功能 |
| 英文描述： | LIN Transceiver |
| 中文描述： | LINE TRANSCEIVER, PDSO8 |
| 封裝： | LEAD FREE, SOIC-8 |
| 文件頁數(shù)： | 11/14頁 |
| 文件大?。?/td> | 92K |
| 代理商： | NCV7380DR2 |
NCV7380
http://onsemi.com
11
Figure 8. Duty Cycle Measurement and Calculation in Accordance to LIN Physical Layer Specification 2.0
V
SUP
TxD
RxD
BUS
GND
t
Bit
t
Bit
100%
t
dom(max)
t
dom(min)
58.1%
28.4%
74.4%
42.2%
t
rec(max)
58.1%
28.4%
t
rec(min)
0%
Duty Cycle Calculation
With the timing parameters shown in Figure 8 two duty
cycles, based on t
rec(min)
and t
rec(max)
can be calculated as
follows:
D1* = t
rec(min)
/(2 x t
Bit
)
D2* = t
rec(max)
/(2 x t
Bit
)
For proper operation at 20 KBit/s (bit time is 50 s) the
LIN driver has to fulfill the duty cycles specified in the AC
characteristics for supply voltages of 7...18 V and the three
defined standard loads.
Due to this simple definition there is no need to measure
slew rates, slope times, transmitter delays and dominant
voltage levels as specified in the LIN physical layer
specification 1.3.
The devices within the D1/D2 duty cycle range also
operates in applications with reduced bus speed of
10.4 KBit/s or below.
In order to minimize EME, the slew rates of the
transmitter can be reduced (by up to
devices have to fulfill the duty cycle definition D3/D4 in
the LIN physical layer specification 2.0. Devices within
this duty cycle range
cannot
operate in higher frequency
20 KBit/s applications.
2 times). Such
*D1 and D2 are defined in the LIN protocol specification 2.0.
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