參數(shù)資料
型號(hào): NCV4299
廠商: ON SEMICONDUCTOR
英文描述: 5.0V Low Drop Fixed Voltage Regulator(5.0V,低壓差固定電壓穩(wěn)壓器)
中文描述: 固定5.0V低壓差穩(wěn)壓器(5.0V,低壓差固定電壓穩(wěn)壓器)
文件頁(yè)數(shù): 16/23頁(yè)
文件大?。?/td> 197K
代理商: NCV4299
NCV4299
http://onsemi.com
16
Reset Output (RO)
A reset signal, Reset Output (RO, low voltage) is
generated as the IC powers up. After the output voltage V
Q
increases above the reset threshold voltage V
RT
, the delay
timer D is started. When the voltage on the delay timer V
D
passes V
UD
, the reset signal RO goes high. A discharge of
the delay timer (V
D
) is started when V
Q
drops and stays
below the reset threshold voltage V
RT
. When the voltage of
the delay timer (V
D
) drops below the lower threshold
voltage V
LD
, the reset output voltage V
RO
is brought low to
reset the processor.
The reset output RO is an open collector NPN transistor,
controlled by a low voltage detection circuit. The circuit is
functionally independent of the rest of the IC, thereby
guaranteeing that RO is valid for V
Q
as low as 1.0 V.
V
I
V
Q
V
D
V
UD
V
RO
V
RT
V
LD
V
RO
,
SAT
t
d
t
RR
< t
RR
t
t
t
t
dV
dt
ID
CD
Power-on-Reset
Thermal
Shutdown
Voltage Dip
at Input
Undervoltage
Secondary
Spike
Overload
at Output
Figure 41. Reset Timing Diagram
Reset Adjust (RADJ)
The reset threshold V
RT
can be decreased from a typical
value of 4.65 V to as low as 3.5 V by using an external
voltage divider connected from the Q lead to the pin RADJ,
as shown in Figures 39 and 40. The resistor divider keeps the
voltage above the V
RADJ,TH
, (typ. 1.35 V), for the desired
input voltages and overrides the internal threshold detector.
Adjust the voltage divider according to the following
relationship:
VTHRES
VRADJ,TH·(RADJ1
RADJ2) RADJ2
(eq. 1)
If the reset adjust option is not needed, the RADJ-pin
should be connected to GND causing the reset threshold to
go to its default value (typ. 4.65 V).
Reset Delay (D)
The reset delay circuit provides a delay (programmable by
capacitor C
D
) on the reset output RO lead. The delay lead D
provides charge current I
D
(typically 8.0 mA) to the external
delay capacitor C
D
during the following times:
1. During Powerup (once the regulation threshold has
been exceeded).
2. After a reset event has occurred and the device
is back in regulation. The delay capacitor is
set to discharge when the regulation (V
RT
, reset
threshold voltage) has been violated. When
the delay capacitor discharges to down to V
LD
,
the reset signal RO pulls low.
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