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參數(shù)資料
| 型號： | NCP5424DG |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Dual Synchronous Buck Controller with Input Current Sharing |
| 中文描述： | 1.5 A DUAL SWITCHING CONTROLLER, 750 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封裝： | LEAD FREE, SOIC-16 |
| 文件頁數(shù)： | 17/18頁 |
| 文件大?。?/td> | 148K |
| 代理商： | NCP5424DG |
NCP5424
http://onsemi.com
17
EMI MANAGEMENT
As a consequence of large currents being turned on and off
at high frequency, switching regulators generate noise as a
consequence of their normal operation. When designing for
compliance with EMI/EMC regulations, additional
components may be added to reduce noise emissions. These
components are not required for regulator operation and
experimental results may allow them to be eliminated. The
input filter inductor may not be required because bulk filter
and bypass capacitors, as well as other loads located on the
board will tend to reduce regulator di/dt effects on the circuit
board and input power supply. Placement of the power
component to minimize routing distance will also help to
reduce emissions.
LAYOUT GUIDELINES
When laying out the CPU buck regulator on a printed
circuit board, the following checklist should be used to
ensure proper operation of the NCP5424.
1. Rapid changes in voltage across parasitic capacitors
and abrupt changes in current in parasitic inductors
are major concerns for a good layout.
2. Keep high currents out of sensitive ground
connections.
3. Avoid ground loops as they pick up noise. Use star or
single point grounding.
4. For high power buck regulators on doublesided
PCB’s a single ground plane (usually the bottom) is
recommended.
5. Even though double sided PCB’s are usually
sufficient for a good layout, fourlayer PCB’s are the
optimum approach to reducing susceptibility to
noise. Use the two internal layers as the power and
GND planes, the top layer for power connections and
component vias, and the bottom layers for the noise
sensitive traces.
6. Keep the inductor switching node small by placing
the output inductor, switching and synchronous FETs
close together.
7. The MOSFET gate traces to the IC must be short,
straight, and wide as possible.
8. Use fewer, but larger output capacitors, keep the
capacitors clustered, and use multiple layer traces
with heavy copper to keep the parasitic resistance
low.
9. Place the switching MOSFET as close to the input
capacitors as possible.
10. Place the output capacitors as close to the load as
possible.
11. Place the COMP capacitor as close as possible to the
COMP pin.
12. Connect the filter components of the following pins:
R
OSC,
V
FB
, V
OUT
, and COMP to the GND pin with a
single trace, and connect this local GND trace to the
output capacitor GND.
13. Place the V
CC
bypass capacitors as close as possible
to the IC.
14. Place the R
OSC
resistor as close as possible to the
R
OSC
pin.
15. Include provisions for 100100pF capacitor across
each resistor of the feedback network to improve
noise immunity and add COMP.
16. Assign the output with lower duty cycle to channel 2,
which has better noise immunity.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| NCP5424DR2 | 功能描述:DC/DC 開關(guān)控制器 Dual Sync. Buck RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開關(guān)頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數(shù)量:1 最大工作溫度:+ 125 C 安裝風(fēng)格: 封裝 / 箱體:CPAK |
| NCP5424DR2G | 功能描述:DC/DC 開關(guān)控制器 Dual Sync. Buck w/Current Sharing RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開關(guān)頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數(shù)量:1 最大工作溫度:+ 125 C 安裝風(fēng)格: 封裝 / 箱體:CPAK |
| NCP5424EVB | 功能描述:電源管理IC開發(fā)工具 ANA SW REG EVAL BRD RoHS:否 制造商:Maxim Integrated 產(chǎn)品:Evaluation Kits 類型:Battery Management 工具用于評估:MAX17710GB 輸入電壓: 輸出電壓:1.8 V |
| NCP5425 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Dual Synchronous Buck Controller |
| NCP5425/D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Dual Synchronous Buck Controller |
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