參數(shù)資料
型號(hào)： NCP5331FTR2G
廠商： ON SEMICONDUCTOR
元件分類： 穩(wěn)壓器
英文描述： Two-Phase PWM Controller with Integrated Gate Drivers
中文描述： 1.5 A SWITCHING CONTROLLER, 750 kHz SWITCHING FREQ-MAX, PQFP32
封裝： LEAD FREE, LQFP-32
文件頁(yè)數(shù)： 21/36頁(yè)
文件大?。?/td> 443K
代理商： NCP5331FTR2G
NCP5331
http://onsemi.com
21
0.25 V and “timing out” at 3 V. The current delivered to the
C
PGD
capacitor (I
PGD
) is a function of the R
OSC
resistor
according to the following equation.
IPGD
0.52 V ROSC
The programmed delay time can be calculated from
tPGD
CPGD
CPGD
(PGDTHRESH
(3.0 V
PGDMIN) IPGD
0.25 V) IPGD
The programmable timer may be disabled (set to 0) by
connecting the C
PGD
pin to 5 V
REF
. This will set the PGD
delay time to the internal delay of 200 s. Figure 26
demonstrates the use of the programmable PGD timer (set
to 6.0 ms) to allow PGD to transition high when V
CORE
is
safely within the regulation limits for the processor (DAC
±
50 mV).
Implementing an Enable Function
An Enable function may be implemented on the NCP5331
in one of two ways. The first method (Method A in
Figure 27) is to pull low on the Ilim pin. This method is the
preferred method, as both the GHx and the GLx pins will be
kept low at turnoff, preventing V
CORE
from being pulled
below ground.
However, if using the “Timed Hiccup Mode Current
Limit” feature with Method A, the Covc pin will time out
when the Ilim pin is pulled low, and the NCP5331 will not
turn back on (after time out) unless the power is recycled.
This can be avoided by adding another transistor to the Covc
pin, thereby keeping it low while the part is disabled.
The second method (Method B in Figure 28) is to pull low
on the NCP5331’s comp pin. With this method, GHx will be
low and GLx will be high while the part is disabled.
However, under Method B, if the part is disabled at
turnon, and if using the “Timed Hiccup Mode Current
Limit” feature, the Covc pin will again time out and the
NCP5331 will not be able to be turned on after the time out
has occurred. This too can be avoided by the use of a
transistor at the Covc pin keeping it low while the part is
disabled.
If using Method B but not with a transistor at the Covc pin,
a 1.0 K resistor must be added between the drain of the
transistor and the Comp pin to prevent the current limit from
being tripped when the Comp pin is quickly pulled low.
I
LIM
Figure 27. Enable Method A
*Needed if using ‘Timed
Hiccup Mode Current Limit’
QI
LIM
BSS123
1
2
3
C
OVC
*QC
OVC
BSS123
2
3
1
Hi to Disable
Lo to Enable
COMP
Figure 28. Enable Method B
QCOMP
BSS123
1
2
3
C
OVC
**QC
OVC
BSS123
2
3
1
Hi to Disable
Lo to Enable
*R
1.0 k
*Needed if not using QCovc
**Allows Disabling at TurnOn
(when using ‘Timed Hiccup Mode Current Limit’)
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