參數(shù)資料
型號(hào)： NCP5331FTR2G
廠商： ON SEMICONDUCTOR
元件分類： 穩(wěn)壓器
英文描述： Two-Phase PWM Controller with Integrated Gate Drivers
中文描述： 1.5 A SWITCHING CONTROLLER, 750 kHz SWITCHING FREQ-MAX, PQFP32
封裝： LEAD FREE, LQFP-32
文件頁(yè)數(shù)： 18/36頁(yè)
文件大?。?/td> 443K
代理商： NCP5331FTR2G
NCP5331
http://onsemi.com
18
Figure 20. Overvoltage Occurs with UVLO Enabled
NOTE:
Using the lower MOSFETs to prevent overvoltage
is not adequate if the MOSFETs are turned OFF at
the UVLO threshold V
CORE
reaches 4.0 V within
100 s.
Figure 21. Overvoltage Occurs with UVLO Disabled
NOTE:
Even if the lower MOSFETs remain ON after
UVLO, there is not enough gate drive voltage to
prevent V
CORE
from reaching 4.0 V.
Overvoltage Protection
The NCP5331 provides a comprehensive level of
overvoltage protection. Overvoltage protection (OVP)
addresses the following five cases (in decreasing level of
difficulty):
1. Normal operation, upper MOSFET shorts
2. Upper MOSFET shorted, turn on the ATX power
3. Normal operation, open the voltage feedback signal
4. Normal operation, ground the voltage feedback
signal
5. Open the voltage feedback signal, apply ATX power
By far the most difficult overvoltage scenario is when the
upper MOSFET shorts during normal operation. The energy
stored in the output filters of both the ATX supply and the
dc/dc converter must be dissipated very quickly or an
overvoltage condition will occur. When the upper MOSFET
shorts, V
CORE
rises and the error amplifier, due to the closed
loop control, will within approximately 400 ns, command
the upper MOSFETs (those that aren’t shorted) to turn OFF
and all the lower MOSFETs to turn ON. This will cause two
things to occur: V
CORE
will stop increasing, and a very high
current will be drawn from the ATX supply. The current
limit in the ATX supply should become active and the input
voltage to the converter will be removed. Now, when the
input voltage drops below the NCP5331’s UVLO threshold
the lower MOSFETs will be turned OFF. At this point, a fair
amount of the energy in the system will have been
dissipated, however, the converter’s output voltage will
begin to rise again as shown in Figure 20. Even if the lower
MOSFETs are
not
turned OFF at the UVLO threshold, as
V
IN
decays, adequate gate drive voltage will not exist to
fully enhance the devices and the CPU may be damaged.
This case is shown in Figure 21.
The NCP5331 avoids the problems with UVLO and the
gate drive voltage. When V
CORE
exceeds 2.05 V, the
NCP5331 will activate an external crowbar MOSFET via
the CB
OUT
pin. This additional MOSFET will clamp V
CORE
and dissipate the remainder of the energy in the system. The
CB
OUT
circuitry is powered by 5 V
SB
and is not disabled
during UVLO. Also, the CB
OUT
pin will always have
adequate gate drive to enhance the lower MOSFET. The
OVP circuits in the NCP5331 are not effected when the ATX
supply current limits and V
IN
is removed. Figure 22 and
Figure 23 document successful operation of the CB
OUT
circuitry when an upper MOSFET is shorted during normal
operation with 0 A and 45 A loading.
The second most difficult overvoltage scenario is when an
upper MOSFET is shorted and the ATX power is applied. In
this case, V
CORE
is equal to V
IN
due to the shorted upper
MOSFET. When V
IN
reaches the maximum rating for the
CPU (2.2 V) adequate gate drive voltage is not available to
enhance the lower MOSFETs or crowbar device enough to
protect the CPU. A typical “Logic Level” MOSFET will
conduct only 100300 A for a gate drive of 2.02.5 V
(R
DS(on)
= 6 k to 25 k ). The R
DS(on)
of the crowbar
device must be lower than 15 m during startup to prevent
damage to the CPU. The NCP5331 avoids this problem by
taking advantage of the 5 V
SB
voltage from the ATX supply.
If V
IN
is less than 5 V
SB
, then 5 V will be used to enhance
the crowbar device. Most modern MOSFETs will be less
than 10 m for a V
GS
greater than 4.5 V. Figure 24 shows
the NCP5331 preventing V
CORE
from exceeding 2.0 V with
a shorted upper MOSFET during startup.
If the voltage feedback signal (COREFB+) is broken, a
high value internal pullup resistor will cause V
FFB
(and
V
FB
) to float higher in voltage. As V
FFB
(and V
FB
) are
pulled higher, the error amplifier will “think” V
CORE
is too
high and command a lower and lower duty cycle until
V
CORE
is driven to 0 V. Without the internal pullup resistor
the error amplifier would command 100% duty cycle and
V
CORE
would be driven very high, damaging the CPU.
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