參數(shù)資料
型號(hào): NCP5331
廠商: ON SEMICONDUCTOR
英文描述: Two-Phase PWM Controller with Integrated Gate Drivers
中文描述: 兩相PWM控制器,帶有集成門(mén)極驅(qū)動(dòng)器
文件頁(yè)數(shù): 29/38頁(yè)
文件大?。?/td> 424K
代理商: NCP5331
NCP5331
http://onsemi.com
29
-
+
+
-
G
VDRP
Σ
R
S1
CS1
C
S1
L1
I
MAX
/2
+
-
G
VDRP
R
S2
CS2
C
S2
L2
I
MAX
/2
CS
REF
COMP
Error
Amp
VID Setting
IBIAS
VFB
R
DRP
R
F1
V
DRP
= VID +
I
MAX
R
L
G
VDRP
V
FB
= VID
V
CORE
I
DRP
I
FBK
V
CORE
= VID - (I
DRP
- IBIAS
VFB
) R
F1
Figure 34. AVP Circuitry at Full-Load
I
DRP
= I
MAX
R
L
G
VDRP
/R
DRP
I
FBK
= I
DRP
- IBIAS
VFB
+ -
Figure 35. V
DRP
Tuning, RC Time Too Long
NOTE:
The RC time constant of the current sense network is
too long (slow); V
DRP
and V
CORE
respond too slowly.
Figure 36. V
DRP
tuning, RC Time Too Short
NOTE:
The RC time constant of the current sense network is
too short (fast); V
DRP
and V
CORE
both overshoot.
7. Current Sensing
For inductive current sensing, choose the current sense
network (RSx, CSx) to satisfy
RSx
CSx
Lo (RL
RPCB)
(32)
For resistive current sensing, choose the current sense
network (RSx, CSx) to satisfy
RSx
CSx
Lo (Rsense)
(33)
This will provide an adequate starting point for RSx and
CSx. After the converter is constructed, the value of RSx
(and/or LSx) should be fine-tuned in the lab by observing
the V
DRP
signal during a step change in load current. Tune
the RSx
CSx network to provide a “square-wave” at the
V
DRP
output pin with maximum rise time and minimal
overshoot as shown in Figures 34 - 36.
Figure 37. V
DRP
Tuning, RC Time Optimal
NOTE:
The RC time constant of the current sense network is
optimal; V
DRP
and V
CORE
respond to the load current
quickly without overshooting.
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