參數(shù)資料
型號(hào)： NCP5331
廠商： ON SEMICONDUCTOR
英文描述： Two-Phase PWM Controller with Integrated Gate Drivers
中文描述： 兩相PWM控制器，帶有集成門極驅(qū)動(dòng)器
文件頁(yè)數(shù)： 15/38頁(yè)
文件大?。?/td> 424K
代理商： NCP5331
NCP5331
http://onsemi.com
15
Figure 15. Enhanced V
2
Control Employing Lossless Inductive Current Sensing and Internal Ramp
+
CSA
-
SWNODE
Lx
RLx
RSx
CSx
COn
CS
REF
+
V
OUT
(V
CORE
)
“Fast-Feedback”
Connection
+
-
PWM
COMP
To F/F
Reset
Channel
Start-Up
Offset
-
+
Error
Amp
DAC
Out
V
FB
COMP
Internal Ramp
x = 1 or 2
- +
V
FFB
CSx
with higher current, the PWM cycle will terminate earlier
providing negative feedback. The NCP5331 provides a CSx
input for each phase, but the CS
REF
and COMP inputs are
common to all phases. Current sharing is accomplished by
referencing all phases to the same CS
REF
and COMP pins,
so that a phase with a larger current signal will turn off earlier
than a phase with a smaller current signal.
Enhanced V
2
responds to disturbances in V
CORE
by
employing both “slow” and “fast” voltage regulation. The
internal error amplifier performs the slow regulation.
Depending on the gain and frequency compensation set by
the amplifier’s external components, the error amplifier will
typically begin to ramp its output to react to changes in the
output voltage in 1-2 PWM cycles. Fast voltage feedback is
implemented by a direct connection from V
CORE
to the
noninverting pin of the PWM comparator via the summation
with the inductor current, internal ramp, and the Startup
OFFSET. A rapid increase in load current will produce a
negative offset at V
CORE
and at the output of the summer.
This will cause the PWM duty cycle to increase almost
instantly. Fast feedback will typically adjust the PWM duty
cycle within 1 PWM cycle.
As shown in Figure 14, an internal ramp (nominally 125 mV
at a 50% duty cycle) is added to the inductor current ramp at
the positive terminal of the PWM comparator. This additional
ramp compensates for propagation time delays from the
current sense amplifier (CSA), the PWM comparator, and the
MOSFET gate drivers. As a result, the minimum ON time of
the controller is reduced and lower duty cycles may be
achieved at higher frequencies. Also, the additional ramp
reduces the reliance on the inductor current ramp and allows
greater flexibility when choosing the output inductor and the
RSxCSx (x = 1 or 2) time constant (see Figure 15) of the
feedback components from V
CORE
to the CSx pin.
Including both current and voltage information in the
feedback signal allows the open loop output impedance of
the power stage to be controlled. When the average output
current is zero, the COMP pin will be
VCOMP
VCORE@ 0 A
Int_Ramp
Channel_Startup_Offset
GCSA
Ext_Ramp 2
Int_Ramp is the internal ramp value at the corresponding
duty cycle, Ext_Ramp is the peak-to-peak external
steady-state ramp at 0 A, G
CSA
is the Current Sense
Amplifier Gain (nominally 2.0 V/V), and the Startup Offset
is typically 0.60 V. The magnitude of the Ext_Ramp can be
calculated from
Ext_Ramp
D
(VIN
VCORE) (RSx
CSx
fSW)
For example, if V
CORE
at 0 A is set to 1.225 V with AVP
and the input voltage is 12.0 V, the duty cycle (D) will be
1.225/12.0 or 10.2%. Int_Ramp will be 125 mV
10.2/50 =
25.5 mV. Realistic values for RSx, CSx and f
SW
are 5.6 k
,
0.1
μ
F, and 200 kHz
using these and the previously
mentioned formula, Ext_Ramp will be 9.8 mV.
VCOMP
1.225 V
2.0 V V
1.855 Vdc.
0.60 V
9.8 mV 2
25.5 mV
If the COMP pin is held steady and the inductor current
changes, there must also be a change in the output voltage.
Or, in a closed loop configuration when the output current
changes, the COMP pin must move to keep the same output
voltage. The required change in the output voltage or COMP
pin depends on the scaling of the current feedback signal and
is calculated as
V
RSx
GCSA
IOUT.
The single-phase power stage output impedance is
Single Stage Impedance
VOUT
IOUT
RS
GCSA
The multiphase power stage output impedance is the
single-phase output impedance divided by the number of
phases. The output impedance of the power stage determines
how the converter will respond during the first few
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