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參數(shù)資料
| 型號： | NCP5318FTR2G |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Two/Three/Four−Phase Buck CPU Controller |
| 中文描述： | SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PQFP32 |
| 封裝： | LEAD FREE, LQFP-32 |
| 文件頁數(shù)： | 19/31頁 |
| 文件大?。?/td> | 384K |
| 代理商： | NCP5318FTR2G |
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NCP5318
http://onsemi.com
19
Since the internally
set thresholds for PWRLS are
V
OUTNo Load
/2 for the lower threshold and V
OUT No Load
+
100 mV for the upper threshold, a simple equation can be
provided to assist the designer in selecting a resistor divider
to provide the desired PWRGD performance.
VLOWER
VOUTNoLoad
2
VOUTNoLoad
R1
R2
R2
VUPPER
100 mV
The logic circuitry inside the chip sets PWRGD low only
after a delay period has been passed. A “power bad” event
does not cause PWRGD to go low unless it is sustained
through the delay time of 1 ms. If the anomaly disappears
before the end of the delay, the PWRGD output will never
be set low. In order to use the PWRGD pin as specified, the
user is advised to connect external resistors as necessary to
limit the current into this pin to 4.0 mA or less.
Undervoltage Lockout
The NCP5318 includes an undervoltage lockout circuit.
This circuit keeps the IC’s output drivers low until V
CC
applied to the IC reaches 9.0 V. The GATE outputs are
disabled when V
CC
drops below 8.0 V.
Soft
Start
At initial power
up, both SS and COMP voltages are zero.
The total SS capacitance will begin to charge with a current
of 70 A. The error amplifier directly charges the COMP
capacitance. An internal clamp ensures that the COMP pin
voltage will always be less than the voltage at the SS pin,
ensuring proper startup behavior. All GATE outputs are held
low until the COMP voltage reaches 0.6 V. Once this
threshold is reached, the GATE outputs are released to
operate normally.
Current Limit
The individual phase currents are summed to compare a
total current signal to a user adjustable voltage on the I
LIM
pin. If the I
LIM
voltage is exceeded, the fault latch trips and
the converter is latched off. V
CC
must be recycled to reset the
latch.
Fault Protection Logic
The NCP5318 includes fault protection circuitry to
prevent harmful modes of operation from occurring. The
fault logic is described in Table 1.
Gate Outputs
The NCP5318 is designed to operate with external gate
drivers. Accordingly, the gate outputs are capable of driving
a 100 pF load with typical rise and fall times of 5.0 ns.
An additional signal, DRVON, works in conjunction with
the Gate Outputs. The DRVON signal is intended to be used
as an enable signal for external gate drivers, such as the
NCP3418B. If the DRVON signal is low, the gate driver will
be disabled and both MOSFETs in the synchronous rectified
phase channel will be held in the off position. If the DRVON
signal is high, the gate driver will be enabled. The high side
MOSFET will be enabled if the Gate Output is high and
DRVON is high. The low side MOSFET will be enabled if
the Gate Output is low and DRVON is high. The DRVON
signal at power up will initially go high as V
CC
rises above
the power on reset (POR) of the IC, roughly 5 V. It will stay
high until the V
CC
voltage exceeds the UVLO threshold of
the part. DRVON will then go to a low state and stay low
until the part is enabled or an OVP is detected.
Digital to Analog Converter (DAC)
The output voltage of the NCP5318 is set by means of a
6
bit, 0.5% DAC. The VID pins must be pulled high
externally. A 1.0 k pullup to a maximum of 3.3 V is
recommended to meet Intel specifications. To ensure valid
logic signals, the designer should ensure at least 800 mV will
be present at the IC for a logic high. The output of the DAC
is described in the Electrical Characteristics section of the
data sheet. These outputs are consistent with VR 10.x and
processor specifications. The DAC output is equal to the
VID code specification minus 19 mV. The latest VR and
processor specifications require a power supply to turn its
output off in the event of a 11111X VID code. When the
DAC sees such a code, the GATE pins stop switching and go
low. This condition is described in Table 1.
Table 1. Description of Fault Logic
Faults
Results
Stop Switching
PWRGD Level
Driver
Enable
SS Character-
istics
Reset Method
Overvoltage Lockout
Yes
High
0.3 mA
Power On
Enable Low
Yes
Depends on output voltage level
Low
0.3 mA
Not Affected
Module Overcurrent Limit
Yes
Depends on output voltage level
Low
0.3 mA
Power On
DAC Code = 11111x
Yes
Depends on output voltage level
Low
0.3 mA
Change VID Code
V
REF
Undervoltage Lockout
Yes
Depends on output voltage level
Low
0.3 mA
Power On
PWRLS Out of Range
No
Low
High
Not Affected
Not Affected
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NCP5322A | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Two−Phase Buck Controller with Integrated Gate Drivers and 5−Bit DAC |
| NCP5322A/D | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Two-Phase Buck Controller with integrated Gate Drivers and 5-Bit DAC |
| NCP5322A_07 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Two−Phase Buck Controller with Integrated Gate Drivers and 5−Bit DAC |
| NCP5322ADW | 功能描述:DC/DC 開關(guān)控制器 2 Phase Buck w/Gate RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開關(guān)頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數(shù)量:1 最大工作溫度:+ 125 C 安裝風格: 封裝 / 箱體:CPAK |
| NCP5322ADWG | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Two−Phase Buck Controller with Integrated Gate Drivers and 5−Bit DAC |
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