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參數(shù)資料
| 型號(hào)： | NCP5214MNR2 |
| 廠商： | ON SEMICONDUCTOR |
| 英文描述： | 2-in-1 Notebook DDR Power Controller |
| 中文描述： | 2合1筆記本DDR電源控制器 |
| 文件頁(yè)數(shù)： | 11/14頁(yè) |
| 文件大?。?/td> | 89K |
| 代理商： | NCP5214MNR2 |
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NCP5214
http://onsemi.com
11
APPLICATION INFORMATION
Overcurrent Protection
The OCP circuit is configured to set the current limit for
the current flowing through the highside FET and
inductor during S0 and S3. The overcurrent tripping level
is programmed by an external resistor RL1 connected
between the OCDDQ pin and drain of the highside FET.
An internal 35 A current sink (IOC) at pin OCDDQ
establishes a voltage drop across the resistor RL1 at a
magnitude of RL1xIOC. Besides, an additional offset
voltage V
OFFSET
of 25 mV is developed at the
noninverting input of the current limit comparator. The
voltage at the noninverting input is then compared to the
voltage at SWDDQ pin when the highside gate drive is
high after a fixed period of blanking time (150 ns) to avoid
false current limit triggering. When the voltage at SWDDQ
is lower than the voltage at the noninverting input of the
current limit comparator for a consecutive 15 internal clock
cycles, an overcurrent condition occurs, during which, all
outputs will be latched off to protect against a
shorttoground condition on SWDDQ or VDDQ. i.e., the
voltage drop across the R
ds(on)
of highside FET developed
by the drain current is larger than the voltage drop across
RL1 plus the additional offset voltage, the OCP is triggered
and the device will be latched off.
The overcurrent protection will trip when a peak inductor
current hit the I
LIMIT
determined by the equation:
RL1
IOC
ILIMIT
VOFFSET
Rds(on)
Since the MOSFET R
ds(on)
varies with temperature as
current flows through the MOSFET increases, the OCP trip
point will also varies with the MOSFET R
ds(on)
temperature variation. The IOC temperature coefficient of
3200 ppm is used to compensate the R
ds(on)
temperature
variation.
To avoid false triggering the overcurrent protection in
normal operating load range, calculate the RL1 value from
the above equation with the following condition:
1. The minimum IOC value from the specification
table,
2. The maximum R
ds(on)
of the MOSFET used at
the highest junction temperature,
3. Determine I
LIMIT
for I
LIMIT
> I
OUT(MAX)
+ I
L
/2.
Besides, a decoupling capacitor C
DCPL
should be added
closed to the lead of the current limit setting resistor RL1
which connected to the drain of the highside MOSFET.
SoftStart
A VDDQ softstart feature is incorporated in the device
to prevent surge current from power supply and output
voltage overshot during power up. When VDDQEN,
VCCA, and VOCDDQ rise above their respective upper
threshold voltages, the external softstart capacitor Css
will be charged up by a constant current source, I
ss
. When
the softstart voltage (Vcss) rises above the SS_EN voltage
(
50 mV), the BGDDQ and TGDDQ will start switching
and VDDQ output will ramp up. When the softstart
voltage reaches the SS_OK voltage (
soft start of VDDQ is finished. The C
ss
will continue to
charge up until it reaches about 2.5 V to 3.0 V.
The softstart time t
ss
can be programmed according to
the following equation:
0.8
Vref + 50 mV), the
tss
Css
Iss
Ceramic capacitors with low tolerance and low
temperature coefficient, such as B, X5R, X7R ceramic
capacitors are recommended to be used as the Css. Ceramic
capacitors with Y5V temperature characteristic are not
recommended.
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