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參數(shù)資料
| 型號(hào)： | NCP1651 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | Single Stage Power Factor Controller |
| 中文描述： | 單級(jí)功率因數(shù)控制器 |
| 文件頁(yè)數(shù)： | 2/8頁(yè) |
| 文件大?。?/td> | 57K |
| 代理商： | NCP1651 |
NCP345
http://onsemi.com
2
Figure 2. Detailed Block Diagram
+
COMP
CNTRL
(3)
OUT
(1)
GND
(2)
+
UVLO
LOGIC
BLOCK
DRIVER
Pre
regulator
V
CC
(5)
IN
(4)
ON/OFF
OUT
V5
R1
R2
R3
R4
Bandgap
Reference
V
V
CC
PIN FUNCTION DESCRIPTIONS
Pin #
Symbol
Pin Description
1
OUT
This signal drives the gate of a Pchannel MOSFET. It is controlled by the voltage level on IN or the logic state
of the CNTRL input. When an overvoltage event is detected, the OUT pin is driven to within 1.0 V of V
CC
in
less than 1.0 sec provided that gate and stray capacitance is less than 12 nF.
2
GND
Circuit Ground
3
CNTRL
This logic signal is used to control the state of OUT and turnon/off the Pchannel MOSFET. A logic High
results in the OUT signal being driven to within 1.0 V of V
CC
which disconnects the FET. If this pin is not used,
the input should be connected to ground.
4
IN
This pin senses an external voltage point. If the voltage on this input rises above the overvoltage threshold
(VTH), the OUT pin will be driven to within 1.0 V of V
CC
, thus disconnecting the FET. The nominal threshold
level is 6.85 V and this threshold level can be increased with the addition of an external resistor between IN
and V
CC
.
5
V
CC
Positive Voltage supply. If V
CC
falls below 2.8 V (nom), the OUT pin will be driven to within 1.0 V of V
CC
, thus
disconnecting the Pchannel FET.
TRUTH TABLE
IN
CNTRL
OUT
<V
th
L
GND
<V
th
H
V
CC
>V
th
L
V
CC
>V
th
H
V
CC
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