參數(shù)資料
型號: NCP1611BDR2G
廠商: ON Semiconductor
文件頁數(shù): 18/29頁
文件大?。?/td> 879K
描述: IC PFC CTLR HE ENHANCED 8-SOIC
標(biāo)準(zhǔn)包裝: 3,000
系列: *
NCP1611
http://onsemi.com
18
TYPICAL CHARACTERISTICS
Figure 57. Blanking Time for Line Range
Detection vs. Temperature
Figure 58. BrownOut Pin Bias Current,
(V
SENSE
 = V
BOH
) vs. Temperature
T
J
, JUNCTION TEMPERATURE (癈)
T
J
, JUNCTION TEMPERATURE (癈)
20
22
24
26
28
30
4
2
1
1
3
5
6
8
110
90
70
30
10
10
30
50
50
130
110
90
70
30
10
10
30
50
50
130
3
0
2
4
7
DETAILED OPERATING DESCRIPTION
Introduction
The NCP1611 is designed to optimize the efficiency of
your PFC stage throughout the load range. In addition, it
incorporates protection features for rugged operation. More
generally, the NCP1611 is ideal in systems where
costeffectiveness, reliability, low standby power and high
efficiency are key requirements:
" Current Controlled Frequency Foldback: the NCP1611
is designed to drive PFC boost stages in socalled
Current Controlled Frequency Foldback (CCFF). In
this mode, the circuit classically operates in Critical
conduction Mode (CrM) when the inductor current
exceeds a programmable value. When the current is
below this preset level, the NCP1611 linearly reduces
the frequency down to about 20 kHz when the current
is zero. CCFF maximizes the efficiency at both nominal
and light load. In particular, standby losses are
reduced to a minimum. Similarly to FCCrM controllers,
an internal circuitry allows nearunity power factor
even when the switching frequency is reduced.
" Skip Mode: to further optimize the efficiency, the
circuit skips cycles near the line zero crossing when the
current is very low. This is to avoid circuit operation
when the power transfer is particularly inefficient at the
cost of current distortion. When superior power factor
is required, this function can be inhibited by offsetting
the FFcontrol pin by 0.75 V.
" Low Startup Current and large V
CC
 range (B version):
The startup consumption of the circuit is minimized to
allow the use of highimpedance startup resistors to
precharge the V
CC
 capacitor. Also, the minimum value
of the UVLO hysteresis is 6 V to avoid the need for
large V
CC
 capacitors and help shorten the startup time
without the need for too dissipative startup elements.
The A version is preferred in applications where the
circuit is fed by an external power source (from an
auxiliary power supply or from a downstream
converter). Its maximum startup level (11.25 V) is set
low enough so that the circuit can be powered from a
12V rail. After startup, the high V
CC
 maximum
rating allows a large operating range from 9.5 V up to
35 V.
" Fast Line / Load Transient Compensation (Dynamic
Response Enhancer): since PFC stages exhibit low loop
bandwidth, abrupt changes in the load or input voltage
(e.g. at startup) may cause excessive over or
undershoot. This circuit limits possible deviations
from the regulation level as follows:
 The NCP1611 linearly decays the power delivery to
zero when the output voltage exceeds 105% of its
desired level (soft OVP). If this soft OVP is too
smooth and the output continues to rise, the circuit
immediately interrupts the power delivery when the
output voltage is 107% above its desired level.
 The NCP1611 dramatically speedsup the regulation
loop when the output voltage goes below 95.5% of
its regulation level. In A version, this function is
enabled only after the PFC stage has startedup to
allow normal softstart operation to occur.
" Safety Protections: the NCP1611 permanently monitors
the input and output voltages, the MOSFET current and
the die temperature to protect the system from possible
overstress making the PFC stage extremely robust and
reliable. In addition to the OVP protection, these
methods of protection are provided:
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