參數(shù)資料
型號: NCP1351BDR2G
廠商: ON SEMICONDUCTOR
元件分類: 穩(wěn)壓器
英文描述: Variable Off Time PWM Controller
中文描述: 0.4 A SWITCHING CONTROLLER, PDSO8
封裝: LEAD FREE, SOIC-8
文件頁數(shù): 13/19頁
文件大小: 222K
代理商: NCP1351BDR2G
NCP1351
http://onsemi.com
13
At this point, the current is fully compressed and remains
frozen. To further decrease the transmitted power, the
frequency does not have other choice than going down.
Figure 14. The NCP1351 Peak Current Compression
Scheme
60 A
80 A
250 A
70 A
40 A
FAULT
(A, B versions)
FB Current
CS Current
Looking to the datasheet specifications, the maximum
peak current is set to 270 A whereas the compressed
current goes down to 70 A. The NCP1351 can thus be
considered as a multi operating mode circuit:
Real fixed peak current / variable frequency mode for
FB current below 60 A.
Then maximum peak current decreases to I
CS,min
over a
narrow linear range of I
FB
(to avoid instability created
by a discrete jump from I
CS,max
to I
CS,min
), between
60 A and 80 A.
Then if
I
FB
keeps on increasing, in a real fixed peak
current/variable frequency mode with reduced peak
current
For biasing purposes and noise immunity improvements,
we recommend to wire a pulldown resistor and a capacitor
in parallel from the FB pin to the controller ground
(Figure 15). Please keep these elements as close as possible
to the circuit. The pulldown resistor increases the
optocoupler current but also plays a role in standby. We
found that a 2.5 k resistor was giving a good tradeoff
between optocoupler operating current (internal pole
position) and standby power.
Figure 15. The Recommended Feedback
Arrangement Around the FB Pin
C1
100nF
V
CC
FB
R1
2.5k
Fault detection
The fault detection circuitry permanently observes the FB
current, as shown on Figure 17. When the feedback current
decreases below 40 A, an external capacitor is charged by
a 11.7 A source. As the voltage rises, a comparator detects
when it reaches 5 V typical. Upon detection, there can be
two different scenarios:
1. A version: the circuit immediately latchesoff and
remains latched until the voltage on the current
into the V
CC
pin drops below a few
μ
A. The latch
is made via an internal SCR circuit who holds Vcc
to around 6 V when fired. As long as the current
flowing through this latch is above a few A, the
circuit remains lockedout. When the user unplugs
the converter, the V
CC
current falls down and
resets the latch.
2. B version: the circuit stops its output pulses and
the auxiliary V
CC
decreases via the controller own
consumption (
600 A). When it touches the
V
CC(min)
point, the circuit restarts and attempts to
crank the power supply. If it fails again, an hiccup
mode takes place (Figure 13).
Figure 16. Hiccup Occurs with the B Version Only,
the A Version Being Latched
V
CC
V
drv
The dutyburst in fault is around 7% in this particular
case.
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