參數(shù)資料
型號(hào): NCP1351
廠商: ON SEMICONDUCTOR
英文描述: Variable Off Time PWM Controller
中文描述: 變關(guān)閉時(shí)間PWM控制器
文件頁數(shù): 7/19頁
文件大?。?/td> 222K
代理商: NCP1351
NCP1351
http://onsemi.com
7
The NCP1351 implements a fixed peak current mode
technique whose regulation scheme implements a variable
switching frequency. As shown on the typical application
diagram, the controller is designed to operate with a
minimum number of external components. It incorporates
the following features:
Frequency Foldback:
Since the switching period
increases when power demand decreases, the switching
frequency naturally diminishes in light load conditions.
This helps to minimize switching losses and offers
good standby power performance.
Very Low Startup Current:
The patented internal
supply block is specially designed to offer a very low
current consumption during startup. It allows the use of
a very high value external startup resistor, greatly
reducing dissipation, improving efficiency and
minimizing standby power consumption.
Natural Frequency Dithering:
The quasifixed t
ON
mode of operation improves the EMI signature since
the switching frequency varies with the natural bulk
ripple voltage.
Peak Current Compression:
As the load becomes
lighter, the frequency decreases and can enter the
audible range. To avoid exciting transformer
mechanical resonances, hence generating acoustic
noise, the NCP1351 includes a patented technique,
which reduces the peak current as power goes down. As
such, inexpensive transformer can be used without
having noise problems.
Negative Primary Current Sensing:
By sensing the
total current, this technique does not modify the
MOSFET driving voltage (V
GS
) while switching.
Furthermore, the programming resistor, together with
the pin capacitance, forms a residual noise filter which
blanks spurious spikes.
Programmable Primary Current Sense
:
It offers a
second peak current adjustment variable, which
improves the design flexibility.
Extended V
CC
Range:
By accepting V
CC
levels up to
28 V, the device offers added flexibility in presence of
loosely coupled transformers. The gate drive is safely
clamped below 20 V to avoid stressing the driven
MOSFET.
Easy OPP:
Connecting a resistor from the CS pin to
the auxiliary winding allows easy bulk voltage
compensation.
Secondary or Primary Regulation:
The feedback
loop arrangement allows simple secondary or primary
side regulation without significant additional external
components.
Latch Input:
If voltage on Pin 7 is externally brought
above 5 V, the controller permanently latches off and
stays latched until the user cycles V
CC
down, below 4
V typically.
Fault Timer:
In presence of badly coupled transformer,
it can be quite difficult to detect an overload or a
shortcircuit on the primary side. When the feedback
current disappears, a current source charges a capacitor
connected to Pin 8. When the voltage on this pin
reaches a certain level, all pulses are shut off and the
V
CC
voltage is pulled down below the VCC
(min)
level.
This protection is latched on the A version (the
controller must be shut down and restart to resume
normal operation), and autorecovery on Version B (if
the fault goes away, the controller automatically
resumes operation).
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