參數(shù)資料
型號: NCP1351
廠商: ON SEMICONDUCTOR
英文描述: Variable Off Time PWM Controller
中文描述: 變關閉時間PWM控制器
文件頁數(shù): 16/19頁
文件大?。?/td> 222K
代理商: NCP1351
NCP1351
http://onsemi.com
16
In this equation, the CCM dutycycle does not exceed
50%. The design should thus be free of subharmonic
oscillations in steadystate conditions. If necessary,
negative ramp compensation is however feasible by the
auxiliary winding.
3. To obtain the primary inductance, we can use the
following equation which expresses the inductance
in relationship to a coefficient k. This coefficient
actually dictates the depth of the CCM operation.
If it goes to 2, then we are in DCM.
(Vin_mindmax)2
FSWKPin
where K = I
L
/I
I
and defines the amount of ripple we want
in CCM (see Figure 20).
Small K: deep CCM, implying a large primary
inductance, a low bandwidth and a large leakage
inductance.
Large K: approaching BCM where the RMS losses are
the worse, but smaller inductance, leading to a better
leakage inductance.
From Equation 16, a K factor of 0.8 (40% ripple) ensures a
good operation over universal mains. It leads to an
inductance of:
43)2
493 H
L
(eq. 21)
L
(100
65 k
0.8
72
(eq. 22)
1.34 A peaktopeak
(eq. 23)
IL
Vin_mindmax
LFSW
19
3
0.8
100
The peak current can be evaluated to be:
Iin_avg
Pout
Vin_min
100
493
0.43
65 k
712 mA
(eq. 24)
Ipeak
Iavg
d
IL
2
0.712
0.43
1.34
2
2.33 A
(eq. 25)
On Figure 20,
I
1
can also be calculated:
IL
2
The valley current is also found to be:
Ivalley
Ipeak
4. Based on the above numbers, we can now evaluate
the RMS current circulating in the MOSFET and
the sense resistor:
II
Ipeak
2.33
1.34
2
1.65 A
(eq. 26)
IL
2.33
u1.34
1.0 A
(eq. 27)
Id_rms
II d
1
1
3
IL
2I1
2
(eq. 28)
1.65
0.65
1
1
3
1.34
2
1.65
2
1.1 A
5. The current peaks to 2.33 A. Selecting a 1 V drop
across the sense resistor, we can compute its value:
1
Ipeak
2.5
Rsense
1
0.4
(eq. 29)
To generate 1 V, the offset resistor will be 3.7 k , as already
explained. Using Equation 28, the power dissipated in the
sense element reaches:
RsenseId_rms2
Psense
0.4
1.12
484 mW
(eq. 30)
6. To switch at 65 kHz, the
C
t
capacitor connected to
pin 2 will be selected to 180 pF.
7. As the load changes, the operating frequency will
automatically adjust to satisfy either equation 5
(high power, CCM) or equation 6 in lighter load
conditions (DCM).
Figure 21 portrays a possible application schematic
implementing what we discussed in the above lines.
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