參數(shù)資料
型號(hào)： NCN6000DTBR2
廠商： ON Semiconductor
文件頁(yè)數(shù)： 9/36頁(yè)
文件大?。?/td> 0K
描述： IC INTERFACE SMART CARD 20TSSOP
產(chǎn)品變化通告： Product Obsolescence 01/Jul/2009
標(biāo)準(zhǔn)包裝： 1
應(yīng)用： ATM 終端，氣泵，ISM
接口： 微控制器
電源電壓： 2.7 V ~ 6 V
封裝/外殼： 20-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 20-TSSOP
包裝： 標(biāo)準(zhǔn)包裝
安裝類型： 表面貼裝
產(chǎn)品目錄頁(yè)面： 1131 (CN2011-ZH PDF)
其它名稱： NCN6000DTBR2OSDKR
NCN6000
http://onsemi.com
17
Transaction Mode
During the transaction mode, the NCN6000 maintains
power supply and clock signal to the card. All the signal
levels related with the card are translated as necessary to
cope with the MPU and the card.
The DCDC converter status and the Vbat state can be
monitored on the STATUS by using the A0 and A1 logic
inputs as depicted in Tables 3 and 4.
Transaction Mode
Logic Conditions:
Card Output:
CS
= L
PWR_ON = H
A0
= H
A1
= H
PGM
= H
I/O
= DATA
TRANSFER
RESET
= H/L
STATUS
= L/H DCDC
status: Fail/Pass?
CRD_VCC = 3.0 or 5.0 V
CRD_CLK = CLOCK
CRD_RST = H/L
CRD_IO
= DATA
TRANSFER
To make sure the data are not polluted by power losses, it
is recommended to check the state of CRD_VCC before
launching a new data transaction. Since CS = L, this is
achieved by forcing bits A0 and A1 according to Table 4, and
reading the STATUS pin 5.
Idle Mode
The idle mode is used when a card is powered up
(CRD_VCC = Vcc), without communication on going.
Idle Mode
Logic Conditions:
Card Output:
CS
= L
PWR_ON = H
A0
= H
A1
= H
PGM
= H
I/O
= Z
RESET
= H
STATUS
= L/H according
to the internal
register results
CRD_VCC = 3.0 or 5.0 V
CRD_CLK = CLOCK active or
L or H
CRD_RST = H
CRD_IO
= Z
In addition, the CRD_CLK signal can be stopped, as
depicted in Tables 3 and 4, to minimize the current
consumption of the external smart card, leaving CRD_VCC
active.
Power Down Operation
The power down mode can be initiated by either the
external MPU (pulling PWR_ON = L) or by one of the
internal error condition (CRD_VCC overload or Vbat Low).
The communication session is terminated immediately,
according to the ISO78163 sequence. On the other hand,
the MPU can run the Standby mode by forced CS = H.
When the card is extracted, the interface shall detect the
operation and run the Power Shut Off of the card as
described by the ISO/CEI 78163 sequence depicted here
after:
ISO78163 sequence:
Force RST to Low
Force CLK to Low, unless it is already in this state
Force CRD_IO to Low
Shut Off the CRD_VCC supply
Since the internal digital filter is activated for any card
insertion or extraction, the physical power sequence will be
activated 150
ms maximum after the card has been extracted.
Of course, such a delay does not exist when the MPU launch
the power down intentionally.
The time delay between each negative going signal is
500 ns typical (Figure 10).
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