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參數(shù)資料
| 型號： | NCN5192MNRG |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 2/13頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC HART MODEM CMOS SGL 32QFN |
| 標準包裝： | 1 |
| 系列： | * |
NCN5192
http://onsemi.com
10
Internal Oscillator Option
The oscillator cell will function with a 460.8 kHz,
921.6 kHz or 1.8432 MHz crystal or ceramic resonator. A
parallel resonant ceramic resonator can be connected
between XIN and XOUT. Figure 11 illustrates the crystal
option for clock generation using a 460.8 kHz (
±1%
tolerance) parallel resonant crystal and two tuning
capacitors Cx. The actual values of the capacitors may
depend on the recommendations of the manufacturer of the
resonator. Typically, capacitors in the range of 100 pF to
470 pF are used. Additionally, a resistor may be required
between XOUT and the crystal terminal, depending on
manufacturer recommendation.
The NCN5192 IC uses CLK2 as clock signal for the wave
shaping and digital logic. This signal must be set 460.8 kHz
by activating the proper frequency division in the internal
register (bit 1 and 2). The CLK1 frequency division (bit 3
and 4) can be freely chosen. This programmable clock signal
can be used to drive other ICs such as a microcontroller and
is not used internally in the NCN5192.
XOUT
XIN
CX
460.8 kHz
Crystal
Oscillator
PC20101118 .5
Figure 11. Crystal Oscillator
External Clock Option
It may be desirable to use an external clock as shown in
Figure 12 rather than the internal oscillator. In addition, the
NCN5192 consumes less current when an external clock is
used. Minimum current consumption occurs with the clock
connected to XOUT and XIN connected to VSS.
XOUT
XIN
Crystal
Oscillator
PC20101118 .6
460.8 kHz
Figure 12. Oscillator with External Clock
Reset
The NCN5192 modem includes a Power on Reset block.
An external resistor division of the supply voltage is
required, and should be tied to pin VPOR. This pin is
attached to an internal comparator, and is compared to the
AREF voltage. When this comparator trips, the RESETB
pin will be pulled low and the IC will reset. After VPOR
returns to a valid level, the RESETB pin will be held low for
at least an additional 35 ms (may be longer depending on
clock frequency). The RESETB pin will also be pulled low
when a microcontroller failure is detected. A watchdog will
guard microcontroller communication by looking at the
KICK pin. When the microcontroller fails to provide a
periodical pulse on this pin, the watchdog will pull down the
RESETB pin for 140
ms. A rising edge should be provided
to the IC at least every 53 ms. A 1.8 kHz kick can also be
provided internally if bit 5 of the internal register is set. If the
watchdog kick is provided internally, the KICK pin should
be tied to Vss.
POR
VPOR
OPA
AREF
KVDE 20110408 .1
VDD
Figure 13. Power on Reset Block
Figure 14. 8 Bit SPI Frame
Figure 15. 16 Bit SPI Frame
SCLK
CS
DATA
SCLK
CS
DATA
SPI Communication
The SPI bus on the NCN5192 is made up of three signals;
DATA, SCLK, and CS. The data is either 8 bits or 16 bits. In
the case of 8 bits CS will go high for eight clock cycles of
SCLK and in the case of 16 bits CS will be high for 16 clock
CS should first go high at least one clock cycle before the
other signals change. One clock cycle is 2.17
ms at a master
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