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參數(shù)資料
| 型號(hào)： | NC7ST08P5 |
| 廠商： | Fairchild Semiconductor |
| 文件頁(yè)數(shù)： | 7/8頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC GATE AND HST 2-INP SC70-5 |
| 產(chǎn)品變化通告： | Mold Compound Change 12/Dec/2007 |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 系列： | 7ST |
| 邏輯類型： | 與門(mén) |
| 電路數(shù)： | 1 |
| 輸入數(shù)： | 2 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 電流 - 靜態(tài)（最大值）： | 1µA |
| 輸出電流高，低： | 2mA，2mA |
| 邏輯電平 - 低： | 0.8V |
| 邏輯電平 - 高： | 2V |
| 額定電壓和最大 CL 時(shí)的最大傳播延遲： | 26ns @ 5.5V，50pF |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 供應(yīng)商設(shè)備封裝： | SC-70-5 |
| 封裝/外殼： | 6-TSSOP（5 引線），SC-88A，SOT-353 |
| 包裝： | 帶卷 (TR) |
2006 Fairchild Semiconductor
www.fairchildsemi.com
FMS6346 Rev. 1.0.5
7
FMS6346
—
Six
Channel,
6th-Order
SD/HD
V
ideo
FIlter
Driver
The same method can be used for biased signals with the
addition of a pull-up resistor to make sure the clamp never
operates. The internal pull-down resistance is 800k
Ω
±20%, so the external resistance should be 7.5M
Ω to set
the DC level to 500mV. If a pull-up resistance less than
7.5M
Ω is desired, an external pull-down can be added
such that the DC input level is set to 500mV.
Figure 16. Biased SCART with DC-Coupled Outputs
The same circuits can be used with AC-coupled outputs if
desired, as shown in Figure 17.
Figure 17 DC-Coupled Inputs, AC-Coupled Outputs
Figure 18. AC-Coupled Inputs, AC-Coupled Outputs
Figure 19. Biased SCART with AC-Coupled Outputs
NOTE: The video tilt or line time distortion is dominated by
the AC-coupling capacitor. The value may need to be in-
creased beyond 220μF to obtain satisfactory operation in
some applications.
Power Dissipation
The FMS6346 output drive conguration must be consid-
ered when calculating overall power dissipation. Care
must be taken not to exceed the maximum die junction
temperature. The following example can be used to calcu-
late the FMS6346’s power dissipation and internal tem-
perature rise:
T
J = TA + Pd θJA
where P
d = PCH1 + PCH2 + PCHx
and P
CHx = Vs ICH - (VO
2
/R
L)
where
V
O = 2Vin + 0.280V
I
CH = (ICC / 6) +
(V
O/RL)
V
IN = RMS value of input signal
I
CC = 60mA
V
s = 5V
R
L = channel load resistance
Board layout can affect thermal characteristics. Refer to
the Layout Considerations section for more information.
Layout Considerations
General layout and supply bypassing play major roles in
high-frequency performance and thermal characteristics.
Fairchild offers a demonstration board, FMS6346DEMO,
to guide layout and aid device testing and characteriza-
tion. The FMS6346DEMO is a four-layer board with a full
power and ground plane. Following this layout congura-
tion provides the optimum performance and thermal char-
acteristics. For best results, follow the steps below as a
basis for high-frequency layout:
Include 10μF and 0.1μF ceramic bypass capacitors
Place the 10μF capacitor within 0.75 inches of the
power pin
Place the 0.1μF capacitor within 0.1 inches of the
power pin
For multi-layer boards, use a large ground plane to
help dissipate heat
For two-layer boards, use a ground plane that extends
beyond the device by at least 0.5 inches
Minimize all trace lengths to reduce series inductances
Output Considerations
The FMS6346 outputs are DC offset from the input by
150mV. Therefore, V
OUT = 2VIN DC+150mV. This offset is
required to obtain optimal performance from the output
driver and is held at the minimum value to decrease the
standing DC current into the load. Since the FMS6346
has a 2x (6dB) gain, the output is typically connected via a
75Ω-series back-matching resistor, followed by the 75Ω
video cable. Due to the inherent divide by two of this con-
guration, the blanking level at the load of the video signal
is always less than 1V. When AC-coupling the output,
ensure that the coupling capacitor of choice passes the
lowest frequency content in the video signal and that line
time distortion (video tilt) is kept as low as possible.
LCVF
Bias
Input
0.1μF
External video
source must
be AC coupled
500mV +/-350mV
75Ω
7.5MΩ
75Ω
DVD or
STB
SoC
DAC
Output
LCVF
Clamp
Inactive
0V - 1.4V
220F
75Ω
DVD or
STB
SoC
DAC
Output
LCVF
Clamp
Active
0.1μF
0V - 1.4V
75Ω
220μF
LCVF
Clamp
Active
0.1
μF
External video
source must
be AC coupled.
500mV +/-350mV
220
μF
75Ω
7.5MΩ
75Ω
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| NC7ST08P5X | 功能描述:邏輯門(mén) 2-Input AND Gate RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時(shí)間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
| NC7ST08P5X_NL | 功能描述:邏輯門(mén) FINISHED GOOD RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時(shí)間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
| NC7ST08P5X_Q | 功能描述:邏輯門(mén) 2-Input AND Gate RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時(shí)間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
| NC7ST32 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:TinyLogic HST 2-Input OR Gate |
| NC7ST32_04 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:TinyLogic HST 2-Input OR Gate |
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