參數(shù)資料
型號(hào): NC7ST08P5
廠商: Fairchild Semiconductor
文件頁(yè)數(shù): 6/8頁(yè)
文件大?。?/td> 0K
描述: IC GATE AND HST 2-INP SC70-5
產(chǎn)品變化通告: Mold Compound Change 12/Dec/2007
標(biāo)準(zhǔn)包裝: 250
系列: 7ST
邏輯類型: 與門
電路數(shù): 1
輸入數(shù): 2
電源電壓: 4.5 V ~ 5.5 V
電流 - 靜態(tài)(最大值): 1µA
輸出電流高,低: 2mA,2mA
邏輯電平 - 低: 0.8V
邏輯電平 - 高: 2V
額定電壓和最大 CL 時(shí)的最大傳播延遲: 26ns @ 5.5V,50pF
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
供應(yīng)商設(shè)備封裝: SC-70-5
封裝/外殼: 6-TSSOP(5 引線),SC-88A,SOT-353
包裝: 帶卷 (TR)
2006 Fairchild Semiconductor
www.fairchildsemi.com
FMS6346 Rev. 1.0.5
6
FMS6346
Six
Channel,
6th-Order
SD/HD
V
ideo
FIlter
Driver
YOUT
Driver
YIN
0.65V
800k
Ω
Applications Information
Functional Description
The FMS6346 Low-Cost Video Filter (LCVF) provides
6dB gain from input to output. In addition, the input is
slightly offset to optimize the output driver performance.
The offset is held to the minimum required value to de-
crease the standing DC current into the load. Typical volt-
age levels are shown in Figure 11.
Figure 11. Typical Voltage Levels
The FMS6346 provides an internal diode clamp to sup-
port AC-coupled input signals. If the input signal does not
go below ground, the input clamp does not operate. This
allows DAC outputs to directly drive the FMS6346 without
an AC coupling capacitor. The worst-case sync tip com-
pression due to the clamp does not exceed 7mV. The in-
put level set by the clamp, combined with the internal DC
offset, keeps the output within its acceptable range. When
the input is AC-coupled, the diode clamp sets the sync tip
(or lowest voltage) just below ground.
For symmetric signals like C, U, V, Cb, Cr, Pb, and Pr; the
average DC bias is fairly constant and the inputs can be
AC-coupled with the addition of a pull-up resistor to set
the DC input voltage. DAC outputs can also drive these
same signals without the AC coupling capacitor. A con-
ceptual illustration of the input clamp circuit is shown in
Figure 12.
Figure 12. Input Clamp Circuit
I/O Congurations
For DC-coupled DAC drive with DC-coupled outputs, use
the conguration shown in Figure 13.
Figure 13. DC-Coupled Inputs and Outputs
If the DAC’s average DC output level causes the signal to
exceed the range of 0V to 1.4V, it can be AC-coupled as
shown in Figure 14.
Figure 14. AC-Coupled Inputs, DC-Coupled Outputs
When the is driven by an unknown external source or a
SCART switch with its own clamping circuitry, the inputs
should be AC-coupled as shown in Figure 15.
Figure 15. SCART Conguration with DC-Coupled
Outputs
There is a 280mV offset from the DC input level to the
DC output level. VOUT = 2 * VIN + 280mV.
0.0 -> 0.02V
0.3 -> 0.32V
0.65 -> 0.67V
1.0 -> 1.02V
VIN
0.28V
0.88V
1.58V
2.28V
Driven by:
DC-Coupled DAC Outputs
AC-Coupled and Clamped
Y, CV, R, G, B
VOUT
0.15V
0.5V
0.85V
VIN
0.58V
1.28V
1.98V
Driven by:
AC-Coupled and Biased
U, V, Pb, Pr, C
VOUT
There is a 280mV offset from the DC input level to the
DC output level. VOUT = 2 * VIN + 280mV.
0.0 -> 0.02V
0.3 -> 0.32V
0.65 -> 0.67V
1.0 -> 1.02V
VIN
0.28V
0.88V
1.58V
2.28V
Driven by:
DC-Coupled DAC Outputs
AC-Coupled and Clamped
Y, CV, R, G, B
VOUT
0.15V
0.5V
0.85V
VIN
0.58V
1.28V
1.98V
Driven by:
AC-Coupled and Biased
U, V, Pb, Pr, C
VOUT
DVD or
STB
SoC
DAC
Output
75Ω
LCVF
Clamp
Inactive
0V - 1.4V
DVD or
STB
SoC
DAC
Output
75Ω
LCVF
Clamp
Inactive
0V - 1.4V
DVD or
STB
SoC
DAC
Output
LCVF
Clamp
Active
0.1μF
0V - 1.4V
75Ω
DVD or
STB
SoC
DAC
Output
LCVF
Clamp
Active
0.1μF
0V - 1.4V
75Ω
LCVF
Clamp
Active
0.1μF
External video
source must
be AC coupled
0V - 1.4V
75Ω
LCVF
Clamp
Active
0.1μF
External video
source must
be AC coupled
0V - 1.4V
75Ω
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