參數(shù)資料
型號(hào): NC7SP38P5X
廠商: Fairchild Semiconductor
文件頁數(shù): 2/11頁
文件大?。?/td> 0K
描述: IC GATE NAND ULP 2INP OD SC70-5
產(chǎn)品變化通告: Mold Compound Change 12/Dec/2007
標(biāo)準(zhǔn)包裝: 3,000
系列: 7SP
邏輯類型: 與非門
電路數(shù): 1
輸入數(shù): 2
特點(diǎn): 開路漏極
電源電壓: 0.9 V ~ 3.6 V
電流 - 靜態(tài)(最大值): 0.9µA
輸出電流高,低: -,2.6mA
邏輯電平 - 低: 0.7 V ~ 0.9 V
邏輯電平 - 高: 1.6 V ~ 2.1 V
額定電壓和最大 CL 時(shí)的最大傳播延遲: 10ns @ 3V ~ 3.6V,30pF
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
供應(yīng)商設(shè)備封裝: SC-70-5
封裝/外殼: 6-TSSOP(5 引線),SC-88A,SOT-353
包裝: 帶卷 (TR)
2004 Fairchild Semiconductor Corporation
www.fairchildsemi.com
NC7SP38 Rev. 1.0.0
10
NC7SP38
Tin
yLogic
ULP
2-Input
NAND
Gate
(Open
Drain
Output)
Physical Dimensions (Continued)
Figure 4. 6-Lead MicroPak, 1.0mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specications do not expand the terms of Fairchild’s worldwide terms and conditions,
specically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
2. DIMENSIONS ARE IN MILLIMETERS
1. CONFORMS TO JEDEC STANDARD M0-252 VARIATION UAAD
MAC06AREVC
Notes:
3. DRAWING CONFORMS TO ASME Y14.5M-1994
TOP VIEW
SIDE VIEW
RECOMMENED
LAND PATTERN
BOTTOM VIEW
1.45
1.00
A
B
0.05 C
2X
0.55 MAX.
0.05 C
(0.49)
(1)
(0.75)
(0.52)
(0.30)
6X
1X
6X
PIN 1
DETAIL A
0.075 X 45
CHAMFER
0.25
0.15
0.35
0.25
0.40
0.30
0.5
(0.05)
1.0
5X
DETAIL A
PIN 1 TERMINAL
0.40
0.30
0.45
0.35
0.10
0.00
0.10
C B A
0.05
C
0.05 C
0.05
0.00
5X
6X
(0.13)
4X
6X
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