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參數(shù)資料

型號(hào)：	NBC12430A
廠商：	ON SEMICONDUCTOR
英文描述：	3.3V/5V Programmable PLL Synthesized Clock Generator(3.3V/5V可編程PLL合成時(shí)鐘發(fā)生器)
中文描述：	3.3V/5V的可編程鎖相環(huán)路合成時(shí)鐘發(fā)生器（3.3V/5V的可編程PLL頻率合成時(shí)鐘發(fā)生器）
文件頁數(shù)：	8/20頁
文件大小：	203K
代理商：	NBC12430A

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NBC12430, NBC12430A

http://onsemi.com

FUNCTIONAL DESCRIPTION

The internal oscillator uses the external quartz crystal as

the basis of its frequency reference. The output of the

reference oscillator is divided by 16 before being sent to the

phase detector. With a 16 MHz crystal, this provides a

reference frequency of 1 MHz. Although this data sheet

illustrates functionality only for a 16 MHz crystal, Table 3,

any crystal in the 10-20 MHz range can be used, Table 5.

The VCO within the PLL operates over a range of 400 to

800 MHz. Its output is scaled by a divider that is configured

by either the serial or parallel interfaces. The output of this

loop divider is also applied to the phase detector.

The phase detector and the loop filter force the VCO

output frequency to be M times the reference frequency by

adjusting the VCO control voltage. Note that for some

values of M (either too high or too low), the PLL will not

achieve loop lock.

The output of the VCO is also passed through an output

divider before being sent to the PECL output driver. This

output divider (N divider) is configured through either the

serial or the parallel interfaces and can provide one of four

division ratios (1, 2, 4, or 8). This divider extends the

performance of the part while providing a 50% duty cycle.

The output driver is driven differentially from the output

divider and is capable of driving a pair of transmission lines

terminated into 50

to V

-2.0 V. The positive reference

for the output driver and the internal logic is separated from

the power supply for the phase-locked loop to minimize

noise induced jitter.

The configuration logic has two sections: serial and

parallel. The parallel interface uses the values at the M[8:0]

and N[1:0] inputs to configure the internal counters.

Normally upon system reset, the P_LOAD input is held

LOW until sometime after power becomes valid. On the

LOW-to-HIGH transition of P_LOAD, the parallel inputs

are captured. The parallel interface has priority over the

serial interface. Internal pullup resistors are provided on the

M[8:0] and N[1:0] inputs to reduce component count in the

application of the chip.

The serial interface logic is implemented with a fourteen

bit shift register scheme. The register shifts once per rising

edge of the S_CLOCK input. The serial input S_DATA must

meet setup and hold timing as specified in the AC

Characteristics section of this document. With P_LOAD

held high, the configuration latches will capture the value of

the shift register on the HIGH-to-LOW edge of the

S_LOAD input. See the programming section for more

information.

The TEST output reflects various internal node values and

is controlled by the T[2:0] bits in the serial data stream. See

the programming section for more information.