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參數(shù)資料
| 型號： | NBC12430A |
| 廠商： | ON SEMICONDUCTOR |
| 英文描述： | 3.3V/5V Programmable PLL Synthesized Clock Generator(3.3V/5V可編程PLL合成時鐘發(fā)生器) |
| 中文描述： | 3.3V/5V的可編程鎖相環(huán)路合成時鐘發(fā)生器（3.3V/5V的可編程PLL頻率合成時鐘發(fā)生器） |
| 文件頁數(shù)： | 13/20頁 |
| 文件大?。?/td> | 203K |
| 代理商： | NBC12430A |
NBC12430, NBC12430A
http://onsemi.com
13
A higher level of attenuation can be achieved by replacing
the resistor with an appropriate valued inductor. Figure 8
shows a 1000 H choke. This value choke will show a
significant impedance at 10 KHz frequencies and above.
Because of the current draw and the voltage that must be
maintained on the PLL_V
CC
pin, a low DC resistance
inductor is required (less than 15
resistor/capacitor filter will be cheaper, easier to implement,
and provide an adequate level of supply filtering.
The
NBC12430
and
sub-nanosecond output edge rates and therefore a good
power supply bypassing scheme is a must. Figure 9 shows
a representative board layout for the NBC12430 and
NBC12430A . There exists many different potential board
layouts and the one pictured is but one. The important aspect
of the layout in Figure 9 is the low impedance connections
between V
CC
and GND for the bypass capacitors.
Combining good quality general purpose chip capacitors
with good PCB layout techniques will produce effective
capacitor resonances at frequencies adequate to supply the
instantaneous switching current for the device outputs. It is
imperative that low inductance chip capacitors are used. It
is equally important that the board layout not introduce any
of the inductance saved by using the leadless capacitors.
Thin interconnect traces between the capacitor and the
power plane should be avoided and multiple large vias
should be used to tie the capacitors to the buried power
planes. Fat interconnect and large vias will help to minimize
layout induced inductance and thus maximize the series
resonant point of the bypass capacitors.
). Generally, the
NBC12430A
provide
ééé
ééé
ééé
ééé
ééé
ééé
ééé
ééé
éé
éé
Figure 9. PCB Board Layout (PLCC-28)
C2
1
C3
XTAL
C1
R1 = 10-15
C1 = 0.01 F
C2 = 22 F
C3 = 0.1 F
éé
éé
éé
CC
= Via
Note the dotted lines circling the crystal oscillator
connection to the device. The oscillator is a series resonant
circuit and the voltage amplitude across the crystal is
relatively small. It is imperative that no actively switching
signals cross under the crystal as crosstalk energy coupled
to these lines could significantly impact the jitter of the
device. Special attention should be paid to the layout of the
crystal to ensure a stable, jitter free interface between the
crystal and the on-board oscillator. Note the provisions for
placing a resistor across the crystal oscillator terminals as
discussed in the crystal oscillator section of this data sheet.
Although the NBC12430 and NBC12430A have several
design features to minimize the susceptibility to power
supply noise (isolated power and grounds and fully
differential PLL), there still may be applications in which
overall performance is being degraded due to system power
supply noise. The power supply filter and bypass schemes
discussed in this section should be adequate to eliminate
power supply noise-related problems in most designs.
Jitter Performance
Jitter is a common parameter associated with clock
generation and distribution. Clock jitter can be defined as the
deviation in a clock's output transition from its ideal
position.
Cycle-to-Cycle Jitter
(short-term) is the period
variation between two adjacent cycles over a defined
number of observed cycles. The number of cycles observed
is application dependent but the JEDEC specification is
1000 cycles.
Figure 10. Cycle-to-Cycle Jitter
T
JITTER(cycle- cycle)
= T
1
- T
0
T
0
T
1
Peak-to-Peak Jitter
is the difference between the
highest and lowest acquired value and is represented as the
width of the Gaussian base.
Figure 11. Peak-to-Peak Jitter
Time
Typical
Gaussian
Distribution
RMS
or one
Sigma
Jitter
J
P
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PDF描述 |
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| NBSG11BA | 2.5V/3.3VSiGe 1:2 Differential Clock Driver with RSECL* Outputs |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NBC12430AFA | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 3.3V/5V Programmable RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| NBC12430AFAG | 功能描述:鎖相環(huán) - PLL 3.3V/5V Programmable PLL Clock Generator RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| NBC12430AFAR2 | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 3.3V/5V Programmable RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| NBC12430AFAR2G | 功能描述:鎖相環(huán) - PLL 3.3V/5V Programmable PLL Clock Generator RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| NBC12430AFN | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 3.3V/5V Programmable RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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