參數(shù)資料
型號: NB7L32M
廠商: ON SEMICONDUCTOR
英文描述: 2.5V/3.3V, 14GHz ÷2 Clock Divider w/CML Output and Internal Termination(w/CML輸出和內(nèi)部終端,2.5V/3.3V, 14GHz ÷2時鐘分頻器)
中文描述: 2.5V/3.3V的,14GHz ÷ 2分頻時鐘瓦特/ CML輸出和內(nèi)部終端(瓦特/白血病輸出和內(nèi)部終端,2.5V/3.3V的,14GHz ÷ 2時鐘分頻器)
文件頁數(shù): 1/11頁
文件大小: 179K
代理商: NB7L32M
Semiconductor Components Industries, LLC, 2005
November, 2005
Rev. 0
1
Publication Order Number:
NB7L32M/D
NB7L32M
2.5V/3.3V, 14GHz
÷
2 Clock
Divider w/CML Output and
Internal Termination
Descriptions
The NB7L32M is an integrated
÷
2 divider with differential clock
inputs and asynchronous reset.
Differential clock inputs incorporate internal 50
resistors and accept LVPECL (Positive ECL), CML, or LVDS. The
high frequency reset pin is asserted on the rising edge. Upon
power
up, the internal flip
flops will attain a random state; the reset
allows for the synchronization of multiple NB7L32M’s in a system.
The differential 16 mA CML output provides matching internal
50 termination which guarantees 400 mV output swing when
externally receiver terminated 50 to V
CC
(See Figure 16).
The device is housed in a small 3x3 mm 16 pin QFN package.
termination
Features
Maximum Input Clock Frequency 14 GHz Typical
200 ps Max Propagation Delay
30 ps Typical Rise and Fall Times
< 0.5 ps Maximum (RMS) Random Clock Jitter
Operating Range: V
CC
= 2.375 V to 3.465 V with V
EE
= 0 V
CML Output Level (400 mV Peak
to
Peak Output), Differential
Output Only
50 Internal Input and Output Termination Resistors
Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP,
EP, and SG Devices
These are Pb
Free Devices
*For additional marking information, refer to
Application Note AND8002/D.
MARKING
DIAGRAM*
A
L
Y
W
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb
Free Package
QFN
16
MN SUFFIX
CASE 485G
http://onsemi.com
16
NB7L
32M
ALYW
1
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
ORDERING INFORMATION
VTCLK
CLK
CLK
VTCLK
50
50
Q
Q
Divide by 2
Reset
R
V
EE
R1
FUNCTIONAL BLOCK DIAGRAM
V
CC
CLK
TRUTH TABLE
x
x
H
Z
W
L
CLK
R
Q
Q
L
÷
2
÷
2
H
Z = LOW to HIGH Transition
W = HIGH to LOW Transition
x = Don’t Care
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