參數(shù)資料
型號: NB7L14MNG
廠商: ON Semiconductor
文件頁數(shù): 1/10頁
文件大小: 0K
描述: IC CLOCK BUFFER 1:4 8GHZ 16-QFN
標(biāo)準(zhǔn)包裝: 123
系列: GigaComm™
類型: 扇出緩沖器(分配)
電路數(shù): 1
比率 - 輸入:輸出: 1:4
差分 - 輸入:輸出: 是/是
輸入: CML,LVCMOS,LVDS,LVPECL,LVTTL
輸出: LVPECL
頻率 - 最大: 8GHz
電源電壓: 2.375 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 16-QFN(3x3)
包裝: 管件
Semiconductor Components Industries, LLC, 2011
May, 2011 Rev. 4
1
Publication Order Number:
NB7L14/D
NB7L14
2.5V / 3.3V 7GHz/10Gbps
Differential 1:4 LVPECL
Fanout Buffer
MultiLevel Inputs w/ Internal
Termination
Description
The NB7L14 is a differential 1:4 LVPECL fanout buffer. The
NB7L14 produces four identical LVPECL output copies of Clock or
Data operating up to 7 GHz or 10.7 Gb/s, respectively. As such, the
NB7L14 is ideal for SONET, GigE, Fiber Channel, Backplane and
other Clock or Data distribution applications.
The differential inputs incorporate internal 50
W termination
resistors that are accessed through the VT Pin. This feature allows the
NB7L14 to accept various logic standards, such as LVPECL, CML,
LVDS, LVCMOS or LVTTL logic levels. The VREFAC reference
output can be used to rebias capacitorcoupled differential or
singleended input signals. The 1:4 fanout design was optimized for
low output skew applications.
The NB7L14 is a member of the GigaComm
family of high
performance clock products.
Features
Input Data Rate > 10.7 Gb/s
Input Clock Frequency > 7 GHz
165 ps Typical Propagation Delay
45 ps Typical Rise and Fall Times
<15 ps max Output Skew
<0.8 ps maximum RMS Clock Jitter
<15 ps pp of Data Dependent Jitter
Differential LVPECL Outputs, 720 mV peaktopeak, typical
LVPECL Operating Range: VCC = 2.375 V to 3.6 V with GND = 0 V
NECL Operating Range: VCC = 0 V with GND = 2.375 V to 3.6 V
Internal Input Termination Resistors, 50 W
VREFAC Reference Output
Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP,
EP, and SG Devices
40°C to +85°C Ambient Operating Temperature
These are PbFree Devices
http://onsemi.com
*For additional marking information, refer to
Application Note AND8002/D.
MARKING
DIAGRAM*
QFN16
MN SUFFIX
CASE 485G
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
ORDERING INFORMATION
(Note: Microdot may be in either location)
16
NB7L
14
ALYWG
G
1
XXXX = Specific Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= PbFree Package
1
Figure 1. Logic Diagram
50 W
IN
VT
IN
Q3
Q2
Q1
Q0
VREFAC
1
QFN16
MN SUFFIX
CASE 485AE
16
7L14
ALYWG
G
1
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