NB7L111M
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3
Table 2. PIN DESCRIPTION
Pin
Name
I/O
Description
15, 24, 27, 39, 42, 51
VCC
Positive supply voltage. All VCC pins must be externally connected to
power supply to guarantee proper operation.
1, 18, 21, 26, 30, 33,
36, 40, 45, 48
VEE
Negative supply voltage. All VEE pins must be externally connected to
power supply to guarantee proper operation.
2
VTCLK0
Internal 50 W termination pin for CLK0. (Note
2)3
CLK0
LVPECL, CML,
LVCMOS, LVTTL,
LVDS Input
Noninverted differential clock/data input 0 (Note
2).4
CLK0
LVPECL, CML,
LVCMOS, LVTTL,
LVDS Input
Inverted differential clock/data input 0 (Note
2).5
VTCLK0
Internal 50 W termination pin for CLK0. (Note
2)6
VTSEL
Internal 50 W termination pin for SEL. (Note
2)7
SEL
LVPECL, CML,
LVCMOS, LVTTL,
LVDS Input
Noninverted differential clock/data select input. Internal 75 kW to VEE.
8
SEL
LVPECL, CML,
LVCMOS, LVTTL,
LVDS Input
Inverted differential clock/data select input. Internal 56 KW to VCC and
56 kW to VEE bias this pin to (VCCVEE)/2.
9
VTSEL
LVPECL, CML,
LVCMOS, LVTTL,
LVDS Input
Internal 50 W termination pin for SEL. (Note
2)10
VTCLK1
Internal 50 W termination pin for CLK1. (Note
2)11
CLK1
LVPECL, CML,
LVCMOS, LVTTL,
LVDS Input
Noninverted differential clock/data input 1 (Note
2).12
CLK1
LVPECL, CML,
LVCMOS, LVTTL,
LVDS Input
Inverted differential clock/data input 1 (Note
2).13
VTCLK1
Internal 50 W termination pin for CLK1. (Note
2)14, 25, 41, 52
NC
17, 20, 23, 29, 32, 35,
38, 44, 47, 50
Q[09]
CML Outputs
Noninverted CML outputs [09] with internal 50 W source termination
16, 19, 22, 28, 31, 34,
37, 43, 46, 49
Q[09]
CML Outputs
Inverted CML outputs [09] with internal 50 W source termination
EP
Exposed Pad (EP). The thermally exposed pad on package bottom (see
case drawing) must be attached to a heatsinking conduit on the printed
circuit board.
1. CML output requires 50 W receiver termination resistor to VCC for proper operation.
2. In the differential configuration when the input termination pin (VTCLK, VTCLK) are connected to a common termination voltage or left open,
and if no signal is applied on CLK and CLK then the device will be susceptible to selfoscillation.