Table 6. AC CHARACTERISTICS VCC = 2.3" />
參數(shù)資料
型號(hào): NB6L14MNG
廠商: ON Semiconductor
文件頁(yè)數(shù): 6/10頁(yè)
文件大小: 0K
描述: IC CLOCK BUFFER 1:4 3GHZ 16-QFN
標(biāo)準(zhǔn)包裝: 123
系列: ECLinPS MAX™
類型: 扇出緩沖器(分配)
電路數(shù): 1
比率 - 輸入:輸出: 1:4
差分 - 輸入:輸出: 是/是
輸入: CML,LVCMOS,LVDS,LVPECL,LVTTL
輸出: LVCMOS,LVPECL
頻率 - 最大: 3GHz
電源電壓: 2.375 V ~ 3.63 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 16-QFN(3x3)
包裝: 管件
產(chǎn)品目錄頁(yè)面: 1115 (CN2011-ZH PDF)
其它名稱: NB6L14MNG-ND
NB6L14MNGOS
NB6L14
http://onsemi.com
5
Table 6. AC CHARACTERISTICS VCC = 2.375 V to 3.63 V, GND = 0 V, TA = 40°C to +85°C (Note 9)
Symbol
Characteristic
Min
Typ
Max
Unit
VOUTPP
Output Voltage Amplitude (@ VINPPmin) (Note 10)
fIN ≤ 1.25 GHz
1.25 GHz ≤ fin ≤ 2.0 GHz
2.0 GHz ≤ fin ≤ 3.0 GHz
550
380
250
700
500
320
mV
fDATA
Maximum Operating Data Rate
2.5
Gb/s
tPD
Propagation Delay
IN to Q
250
370
500
ps
tS
SetUp Time (Note 11)
EN to IN, IN
300
ps
tH
Hold Time (Note 11)
EN to IN, IN
300
ps
tSKEW
WithinDevice Skew (Note 12)
Device to Device Skew (Note 13)
5.0
20
150
ps
tJITTER
RMS Random Jitter (Note 14)
fIN = 2.5 GHz
PeaktoPeak Data Dependent Jitter
(Note 15)
fDATA = 2.5 Gb/s
14
1.0
ps
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 10)
100
VCC GND
mV
tr,tf
Output Rise/Fall Times @ Full Output Swing
(20%80%)
70
150
200
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
9. Measured by forcing VINPP (min) from a 50% duty cycle clock source. All loading with an external RL = 50 W to VCC – 2.0 V. Input edge rates
40 ps (20%80%).
10.Input and output voltage swing is a singleended measurement operating in differential mode.
11. Setup and hold times apply to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous
applications, setup and hold times do not apply.
12.Within device skew is measured between two different outputs under identical power supply, temperature and input conditions.
13.Device to device skew is measured between outputs under identical transition @ 0.5 GHz.
14.Additive RMS jitter with 50% duty cycle clock signal.
15.Additive peaktopeak data dependent jitter with input NRZ data at PRBS 2^231 and K28.5 at 2.5Gb/s.
800
700
600
500
400
300
200
100
0
01
2
3
fout, CLOCK OUTPUT FREQUENCY (GHz)
V
OUTP
P
OUTPUT
VOL
TAGE
AMPLITUDE
(mV)
(TYPICAL)
Figure 4. Output Voltage Amplitude (VOUTPP) versus Output
Frequency at Ambient Temperature (Typical)
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