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參數(shù)資料
| 型號(hào)： | NB4N441MNG |
| 廠(chǎng)商： | ON Semiconductor |
| 文件頁(yè)數(shù)： | 11/12頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC SYNTH PLL CLK LVPECL 24-QFN |
| 標(biāo)準(zhǔn)包裝： | 92 |
| 類(lèi)型： | 時(shí)鐘/頻率合成器 |
| PLL： | 是 |
| 輸入： | LVCMOS，LVTTL，晶體 |
| 輸出： | LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 425MHz |
| 除法器/乘法器： | 無(wú)/無(wú) |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤(pán) |
| 供應(yīng)商設(shè)備封裝： | 24-QFN（4x4） |
| 包裝： | 管件 |
NB4N441
http://onsemi.com
8
Figure 4. Power Supply Filter
PLL_VCC
VCC
0.01 mF
47 mF
L=1000 mH
R=15 W
0.01 mF
3.3 V or
5.0 V
RS = 5 W
3.3 V or
5.0 V
Power Supply Filtering
The NB4N441 is a mixed analog/digital product and as
such, it exhibits some sensitivities that would not necessarily
be seen on a fully digital product. Analog circuitry is
naturally susceptible to random noise, especially if this noise
is seen on the power supply pins. The NB4N441 provides
separate power supplies for the digital circuitry (VCC) and
the internal PLL (PLL_VCC) of the device. The purpose of
this design technique is to try and isolate the high switching
noise of the digital outputs from the relatively sensitive
internal analog phaselocked loop. In a controlled
environment such as an evaluation board, this level of
isolation is sufficient. However, in a digital system
environment where it is more difficult to minimize noise on
the power supplies, a second level of isolation may be
required. The simplest form of isolation is a power supply
illustrates a typical power supply filter scheme. The
NB4N441 is most susceptible to noise with spectral content
in the 1 kHz to 1 MHz range. Therefore, the filter should be
designed to target this range. The key parameter that needs
to be met in the final filter design is the DC voltage drop that
will be seen between the VCC supply and the PLL_VCC pin
of the NB4N441. From the data sheet, the PLL_VCC current
(the current sourced through the PLL_VCC Pin) is typically
26 mA. Assuming that a minimum of 2.9 V must be
maintained on the PLL_VCC pin, very little DC voltage drop
can be tolerated when a 3.3 V VCC supply is used. The
resistor shown in Figure 4 must have a resistance of 5
W
Max to meet the voltage drop criteria. The RC filter pictured
will provide a broadband filter with approximately 100:1
attenuation for noise whose spectral content is above
20 kHz. As the noise frequency crosses the series resonant
point of an individual capacitor, it’s overall impedance
begins to look inductive and thus increases with increasing
frequency. The parallel capacitor combination shown
ensures that a low impedance path to ground exists for
frequencies well above the bandwidth of the PLL. The level
of required filtering is subject to further optimization and
simplification. All the VCC pins are connected to the same
VCC plane. All the ground pins (GND) are connected to the
same GND plane.
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參數(shù)描述 |
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| NB4N441MNGEVB | 功能描述:BOARD EVAL NB4N441MNG RoHS:是 類(lèi)別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:* 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電源管理，電池充電器 嵌入式:否 已用 IC / 零件:MAX8903A 主要屬性:1 芯鋰離子電池 次要屬性:狀態(tài) LED 已供物品:板 |
| NB4N441MNR2G | 功能描述:鎖相環(huán) - PLL MLTPRTCL PLL CLK SYN RoHS:否 制造商:Silicon Labs 類(lèi)型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| NB4N507A | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:3.3V/5V, 50 MHz to 200 MHz PECL Clock Synthesizer |
| NB4N507A_06 | 制造商:ONSEMI 制造商全稱(chēng):ON Semiconductor 功能描述:3.3V/5V, 50 MHz to 200 MHz PECL Clock Synthesizer |
| NB4N507AD | 功能描述:鎖相環(huán) - PLL 3.3V/5V PECL Clock RoHS:否 制造商:Silicon Labs 類(lèi)型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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