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參數(shù)資料
| 型號： | NB4N855SMR4G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 1/9頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DRVR/RCVR/BUFF/XLATOR MICRO10 |
| 標準包裝： | 1 |
| 邏輯類型： | 接收器，驅(qū)動器，緩沖器，變換器 |
| 位數(shù)： | 2 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 剪切帶 (CT) |
| 其它名稱： | NB4N855SMR4GOSCT |
Semiconductor Components Industries, LLC, 2011
June, 2011 Rev. 4
1
Publication Order Number:
NB4N855S/D
NB4N855S
3.3 V, 1.5 Gb/s Dual
AnyLevel to LVDS
Receiver/Driver/Buffer/
Translator
Description
NB4N855S is a clock or data Receiver/Driver/Buffer/Translator
capable of translating AnyLevel input signal (LVPECL, CML, HSTL,
LVDS, or LVTTL/LVCMOS) to LVDS. Depending on the distance,
noise immunity of the system design, and transmission line media, this
device will receive, drive or translate data or clock signals up to
1.5 Gb/s or 1.0 GHz, respectively. This device is pinforpin plug in
compatible to the SY55855V in a 3.3 V applications.
The NB4N855S has a wide input common mode range of
GND + 50 mV to VCC 50 mV. This feature is ideal for translating
differential or singleended data or clock signals to 350 mV typical
LVDS output levels.
The device is offered in a small 10 lead MSOP package. NB4N855S
is targeted for data, wireless and telecom applications as well as high
speed logic interface where jitter and package size are main
requirements.
Application notes, models, and support documentation are available
at www.onsemi.com.
Features
Guaranteed Input Clock Frequency up to 1.0 GHz
Guaranteed Input Data Rate up to 1.5 Gb/s
490 ps Maximum Propagation Delay
1.0 ps Maximum RMS Jitter
180 ps Maximum Rise/Fall Times
Single Power Supply; VCC = 3.3 V ±10%
Temperature Compensated TIA/EIA644 Compliant LVDS Outputs
GND + 50 mV to VCC 50 mV VCMR Range
This is a PbFree Device
Figure 1. Typical Output Waveform at 1.5 Gb/s with K28.5
(VINPP = 100 mV, Input Signal DDJ = 24 ps)
Device DDJ = 7 ps
TIME (133 ps/div)
VOL
TAGE
(50
mV/div)
A
= Assembly Location
Y
= Year
W
= Work Week
G
= PbFree Package
*For additional marking information, refer to
Application Note AND8002/D.
MARKING
DIAGRAM*
Micro10
M SUFFIX
CASE 846B
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
ORDERING INFORMATION
Q0
Functional Block Diagram
D0
Q1
D0
D1
1
10
1
855S
AYWG
G
(Note: Microdot may be in either location)
相關(guān)PDF資料 |
PDF描述 |
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| NB6HQ14MMNG | IC CLK BUFF MUX 1:4 5GHZ 16-QFN |
| NB6L11DTR2 | IC CLK BUFFER TRANSLA 1:2 8TSSOP |
| NB6L11SMNR2G | IC CLK BUFFER TRANSLA 1:2 16-QFN |
| NB6L14MNG | IC CLOCK BUFFER 1:4 3GHZ 16-QFN |
| NB6L14MNR2G | IC CLOCK BUFFER 1:4 3GHZ 16-QFN |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NB50SI/12-C-D | 制造商:Martek Power Inc 功能描述:50W 12V OUT 28V IN DC/DC - Bulk |
| NB50SI/15-C-D | 制造商:Martek Power Inc 功能描述:50W 15V OUT 28V IN DC/DC - Bulk |
| NB50SI/24-C-D | 制造商:Martek Power Inc 功能描述:50W 24V OUT 28V IN DC/DC - Bulk |
| NB50SI/3.3-B | 制造商:Martek Power Inc 功能描述:50W 3.3V OUT 28V IN DC/DC - Bulk |
| NB50SI/3.3-B-I | 制造商:Martek Power Inc 功能描述:50W 3.3V OUT 28V IN DC/DC - Bulk |
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