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參數(shù)資料
| 型號(hào)： | NB4L7210MNG |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 7/11頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK BUFF MUX 2:10 2GHZ 52-QFN |
| 標(biāo)準(zhǔn)包裝： | 260 |
| 類型： | 扇出緩沖器（分配），多路復(fù)用器 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:10 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | CML，LVCMOS，LVDS，LVPECL，LVTTL |
| 輸出： | LVPECL |
| 頻率 - 最大： | 2GHz |
| 電源電壓： | 2.375 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 52-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 52-QFN（8x8） |
| 包裝： | 托盤 |
NB4L7210
http://onsemi.com
5
Symbol
Characteristic
Min
Typ
Max
Unit
VOUTPP Output Voltage Amplitude @ VINPPmin (See Figure 9)
fin = 100 MHz
fin = 1 GHz
650
530
800
790
875
960
mV
tPLH,
tPHL
Propagation Delay to (See Figure 9)
CLK/CLK to Qx/Qx (Note 7)
SCLK to SDATAOUT Measured at 1.5 V
610
6.5
725
20
875
30.8
ps
ns
tSKEW
Duty Cycle Skew (Note 8)
Within Device Skew
Device to Device Skew (Note 8)
5
0
2
5
20
10
35
200
ps
ts
Setup Time
SDATA to SCLK Measured at 1.5 V
SCLK to SLOAD+ Measured at 1.5 V
150
1000
115
ps
Th
Hold Time
SDATA to SCLK
325
345
365
ps
PWmin
Minimum Pulse Width
SLOAD
2.0
ns
tJIT()
RMS Phase Jitter, Integration Range 12 KHz to 20 MHz
@155.52 MHz
@ 622.08 MHz
See Fig 10
See Fig 11
fs
tJITTER
TIE Rj (10,000 Cycles)
@155.52 MHz
@ 622.08 MHz
Crosstalk RMS Jitter RMS (1000 Cycles) (Note 9)
1.7
0.63
3.9
ps
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration, measured Singleended on each input)
150
750
1200
mV
tr , tf
Output Risetime and Falltime
Qx/Qx (20% to 80%)
SDATAOUT (0.8 V 2.0 V)
120
0.88
185
10
260
15
ps
ns
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
6. Measured by forcing VINPP (Typ 750 mVPP) from a 50% duty cycle clock source. Q/Q Outputs loaded with 50 W to VCC 2.0 V (See Figure 16).
SCLK, SDATA and SLOAD at LOW SDATAOUT loaded 20 kW and 15 pF to GND.
7. Measured from the input pair crosspoint to each single output pair crosspoint.
8. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw and Tpw+.
9. 155.52 MHz @ 750 mVPP input on measured output, 161.13 MHz @ 850 mVPP input on all other others.
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