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參數(shù)資料
| 型號： | NB3RL02FCT2G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK BUFFER 1:2 52MHZ 8-WLCSP |
| 標準包裝： | 1 |
| 類型： | 扇出緩沖器（分配） |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 無/無 |
| 輸入： | 時鐘 |
| 輸出： | LVCMOS |
| 頻率 - 最大： | 52MHz |
| 電源電壓： | 2.3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-WFBGA，WLCSP |
| 供應(yīng)商設(shè)備封裝： | 8-WLCSP（1.57x.77） |
| 包裝： | 標準包裝 |
| 其它名稱： | NB3RL02FCT2GOSDKR |
Semiconductor Components Industries, LLC, 2013
October, 2013 Rev. 2
1
Publication Order Number:
NB3RL02/D
NB3RL02
Low Phase-Noise
Two-Channel Clock Fanout
Buffer
The NB3RL02 is a lowskew, low jitter 1:2 clock fanout buffer,
ideal for use in portable endequipment, such as mobile phones. With
integrated LDO and output control circuitry.
The MCLK_IN pin has an AC coupling capacitor and will directly
accept a square or sine wave clock input, such as a temperature
compensated crystal oscillator (TCXO). The minimum acceptable
input amplitude of the sine wave is 300 mV peaktopeak.
The two clock outputs are enabled by control inputs CLK_REQ1
and CLK_REQ2.
The NB3RL02 has an integrated LowDropOut (LDO) voltage
regulator which accepts input voltages from 2.3 V to 5.5 V and outputs
1.8 V at Iout = 50 mA. This 1.8 V supply is externally available to
provide regulated power to peripheral devices, such as a TCXO.
The adaptive clock output buffers offer controlled slewrate over a
wide capacitive loading range which minimizes EMI emissions,
maintains signal integrity, and minimizes ringing caused by signal
reflections on the clock distribution lines.
The NB3RL02 is offered in a 0.4 mm pitch waferlevelchipscale
(WLCS) package and is optimized for very low standby current
consumption.
Features
Low Additive Noise:
149 dBc/Hz at 10 kHz Offset Phase Noise
0.37 ps (rms) Output Jitter
Limited Output Slew Rate for EMI Reduction
(1 ns to 5 ns/Rise/Fall Time for 1050 pF Loads)
Regulated 1.8 V Output Supply Available for External Clock Source,
ie. TCX0
UltraSmall Package:
8ball: 0.4 mm Pitch WLCS
ESD Performance Exceeds JESD 22
2000 V HumanBody Model (A114A)
200 V Machine Model (A115A)
1000 V ChargedDevice Model (JESD22C101A Level III)
These are PbFree Devices
Applications
Cellular Phones
Global Positioning Systems (GPS)
WLCSP8
CASE 499BQ
MARKING
DIAGRAMS
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
ORDERING INFORMATION
RL
= Specific Device Code
YY
= Year
WW
= Work Week
G
= PbFree Package
RLYYWW
G
LOGIC DIAGRAM
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