參數(shù)資料
型號： NB3N853531EDTG
廠商： ON Semiconductor
文件頁數(shù)： 4/9頁
文件大?。?/td> 0K
描述： IC FANOUT BUFFER LVPECL 20TSSOP
標準包裝： 75
類型： 扇出緩沖器（分配），多路復(fù)用器
電路數(shù)： 1
比率 - 輸入:輸出： 2:4
差分 - 輸入:輸出： 無/是
輸入： LVCMOS，LVTTL，晶體
輸出： LVPECL
頻率 - 最大： 266MHz
電源電壓： 3.135 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 20-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 20-TSSOP
包裝： 管件
NB3N853531E
http://onsemi.com
4
Table 5. CRYSTAL CHARACTERISTICS AND CONNECTIONS
Parameter
Min
Typ
Max
Unit
Mode of Oscillation
Fundamental Parallel
Frequency
12
40
MHz
Equivalent Series Resistance (ESR)
50
W
Shunt Capacitance
7
pF
Drive Level
1
mW
Table 6. DC CHARACTERISTICS VCC = 3.3 ±5% V (3.135 to 3.465 V), VEE = 0 V, TA = 40°C to +85°C (Note 5)
Symbol
Characteristic
Min
Typ
Max
Unit
IEE
Power Supply Current
60
mA
VIH
Input HIGH Voltage
2
VCC + 0.3
V
VIL
Input LOW Voltage
0.3
0.8
V
IIH
Input High Current (VCC = 3.456 V)
CLK, CLK_SEL = 3.456 V
CLK_EN = 3.456 V
150
5
mA
IIL
Input LOW Current (VCC = 3.456 V)
CLK, CLK_SEL = 3.456 V
CLK_EN = 3.456 V
5
150
mA
VOH
Output HIGH Voltage
VCC 1.4
VCC 0.9
V
VOL
Output LOW Voltage
VCC 2.0
VCC 1.7
V
VOUTSWING Output Voltage Swing (peaktopeak)
0.6
1.0
V
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Outputs terminated 50 W to VCC 2.0 V, see Figure 4.
Table 7. AC CHARACTERISTICS VCC = 3.3 ±5% V (3.135 to 3.465 V), VEE = 0 V, TA = 40°C to +85°C (Note 6)
Symbol
Characteristic
Min
Typ
Max
Unit
FMAX
Maximum Operating Frequency
0
266
MHz
tPD
Propagation Delay (Notes 7 and 9)
1.1
1.8
ns
tSKEWDC
Duty Cycle Skew same path similar conditions at 50 MHz (Notes 7, 8 and 9)
46
54
%
tSKEWOO
Output to Output Skew Within A Device (Notes 7, 8 and 9)
30
ps
tSKEWDD
Device to Device Skew similar path and conditions (Notes 7, 8 and 9)
200
ps
tJIT
Additive Phase Noise Jitter (RMS) @ 155.52 MHz (Integrated from 12 kHz to
20 MHz) See Figure 6. (Note 9)
0.053
ps
tr/tf
Output rise and fall times (20% and 80% points) (Note 9)
225
600
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
6. Outputs terminated 50 W to VCC 2.0 V, see Figure 4.
7. Measured under the same supply voltage, output loading, and input conditions.
8. Similar conditions.
9. Limits do not apply to overdriving XTAL_IN.
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