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參數(shù)資料
| 型號(hào)： | NB3N551MNR4G |
| 廠商： | ON Semiconductor |
| 文件頁(yè)數(shù)： | 1/7頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK BUFFER 1:4 180MHZ 8-DFN |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 扇出緩沖器（分配） |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:4 |
| 差分 - 輸入:輸出： | 無(wú)/無(wú) |
| 輸入： | LVCMOS，LVTTL |
| 輸出： | LVCMOS，LVTTL |
| 頻率 - 最大： | 180MHz |
| 電源電壓： | 3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-VFDFN 裸露焊盤(pán) |
| 供應(yīng)商設(shè)備封裝： | 8-DFN（2x2） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | NB3N551MNR4G-ND NB3N551MNR4GOSTR |
Semiconductor Components Industries, LLC, 2012
July, 2012 Rev. 4
1
Publication Order Number:
NB3N551/D
NB3N551
3.3 V / 5.0 V
Ultra-Low Skew
1:4 Clock Fanout Buffer
Description
The NB3N551 is a low skew 1to 4 clock fanout buffer, designed
for clock distribution in mind. The NB3N551 specifically guarantees
low outputtooutput skew. Optimal design, layout and processing
minimize skew within a device and from device to device.
The output enable (OE) pin threestates the outputs when low.
Features
Input/Output Clock Frequency up to 180 MHz
Low Skew Outputs (50 ps typical)
RMS Phase Jitter (12 kHz – 20 MHz): 43 fs (Typical)
Output goes to ThreeState Mode via OE
Operating Range: VDD = 3.0 V to 5.5 V
Ideal for Networking Clocks
Packaged in 8pin SOIC
Industrial Temperature Range
These are PbFree Devices
Figure 1. Block Diagram
CLK
Q1
Q2
Q3
Q4
OE
Device
Package
Shipping
ORDERING INFORMATION
NB3N551DG
SOIC8
(PbFree)
98 Units/Rail
SOIC8
D SUFFIX
CASE 751
MARKING
DIAGRAMS*
http://onsemi.com
1
8
3N551 = Specific Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= PbFree Package
3N551
ALYW
G
1
8
NB3N551DR2G
SOIC8
(PbFree)
2500/Tape & Reel
For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Q4
GND
VDD
OE
ICLK
Q1
Q2
Q3
PIN CONNECTIONS
1
DFN8
MN SUFFIX
CASE 506AA
6K = Specific Device Code
M
= Date Code
G
= PbFree Package
6K
M
G
14
NB3N551MNR4G
DFN8
(PbFree)
1000/Tape & Reel
(Note: Microdot may be in either location)
1
2
3
4
8
7
6
5
*For additional marking information, refer to
Application Note AND8002/D.
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