Table 5. AC CHARACTERISTICS VDD = " />
參數(shù)資料
型號(hào): NB3N3010BDR2G
廠商: ON Semiconductor
文件頁(yè)數(shù): 4/9頁(yè)
文件大小: 0K
描述: IC CLOCK GENERATOR PLL 8SOIC
標(biāo)準(zhǔn)包裝: 2,500
類型: 時(shí)鐘/頻率發(fā)生器
PLL:
主要目的: USB 應(yīng)用
輸入: 時(shí)鐘
輸出: LVCMOS
電路數(shù): 1
比率 - 輸入:輸出: 1:2
差分 - 輸入:輸出: 無/無
頻率 - 最大: 12.288MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: 0°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOICN
包裝: 帶卷 (TR)
NB3N3010B
http://onsemi.com
4
Table 5. AC CHARACTERISTICS VDD = 3.3 V $5%, GND = 0 V, TA = 0°C to +85°C (Note 4)
Symbol
Characteristic
Min
Typ
Max
Unit
fout
Output Clock Frequency: CLKA & CLKB
fOUT = 8 kHz x 1536
S0 = 1
fOUT = 4 kHz x 3072
S0 = 0
12.25728
12.288
12.31872
MHz
fREF
Reference Input Frequency
S0 = 1
S0 = 0
7.98
3.99
8
4
8.02
4.01
kHz
tjit(per)ref
Reference Input Period Jitter (pkpk)
250
ns
tREFH
Reference Input Pulse Width (high)
S0 = 1
S0 = 0
33
68000
136000
ns
tCLKH
CLKA, CLKB output width, high
13
ns
tCLKL
CLKA, CLKB output width, low
13
ns
tr
CLKA, CLKB rise time 10% 90%
4
ns
tf
CLKA, CLKB fall time 90% 10%
4
ns
tjit(per)
CLKA, CLKB period jitter (over 10k cycles)
peaktopeak
RMS
250
20
ps
tjit(cc)
CLK_A, CLKB cycletocycle jitter (1k cycles)
peaktopeak
RMS
300
35
ps
tsk(LH)
CLKA to CLKB output skew (lowtohigh transitions)
700
ps
tsk(HL)
CLKA to CLKB output skew (hightolow transitions)
700
ps
Power Valid to ENABLEn
10
ms
ENABLEn to CLKA/CLKB
50
100
ms
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Outputs loaded with 15 pF max to ground. CFILT capacitor must be installed; see Figure 4.
5. Maximum time required after power is applied to the MCLK FLL until it is ready to accept ENABLEn active.
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