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參數(shù)資料
| 型號： | NB100LVEP91 |
| 廠商： | ON SEMICONDUCTOR |
| 英文描述： | 2.5V / 3.3V Any Level Positive Input to -2.5V -3.3V / -5V NECL Output Translator |
| 中文描述： | 為2.5V / 3.3V的任何級別的積極投入到為2.5V至3.3V / - 5V的輸出翻譯NECL |
| 文件頁數(shù)： | 1/14頁 |
| 文件大小： | 153K |
| 代理商： | NB100LVEP91 |
Semiconductor Components Industries, LLC, 2004
December, 2004
Rev. 5
1
Publication Order Number:
NB100LVEP56/D
NB100LVEP56
2.5V / 3.3V / 5VECL Dual
Differential 2:1 Multiplexer
The NB100LVEP56 is a dual, fully differential 2:1 multiplexer. The
differential data path makes the device ideal for multiplexing low
skew clock or differential data signals. The device features both
individual and common select inputs to address both data path and
random logic applications. Common and individual selects can accept
both ECL and CMOS input voltage levels. Multiple V
BB
pins are
provided.
The V
BB
pin, an internally generated voltage supply, is available to
this device only. For single
ended input operation, the unused
differential input is connected to V
BB
as a switching reference voltage.
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a 0.01 F capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V
BB
should be left open.
Maximum Input Clock Frequency > 2.5 GHz Typical
Maximum Input Data Rate > 2.5 Gb/s Typical
525 ps Typical Propagation Delays
Low Profile QFN Package
PECL Mode Operating Range:
V
CC
= 2.375 V to 5.5 V with V
EE
= 0 V
NECL Mode Operating Range:
V
CC
= 0 V with V
EE
=
2.375 V to
5.5 V
Separate, Common Select, and Individual Select
(Compatible with ECL and CMOS Input Voltage Levels)
Q Output Will Default LOW with Inputs Open or at V
EE
Multiple V
BB
Outputs
Pb
Free Packages are Available*
*For additional information on our Pb
Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
TSSOP
20
DT SUFFIX
CASE 948E
MARKING
DIAGRAMS*
*For additional information, see Application Note
AND8002/D
N100
VP56
ALYW
20
1
1
20
A = Assembly Location
L
= Wafer Lot
Y = Year
W = Work Week
N100
VP56
ALYW
1
24
QFN
24
MN SUFFIX
CASE 485L
24
1
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
ORDERING INFORMATION
http://onsemi.com
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| NB100LVEP91DW | 2.5V / 3.3V Any Level Positive Input to -2.5V -3.3V / -5V NECL Output Translator |
| NB100LVEP91DWR2 | 2.5V / 3.3V Any Level Positive Input to -2.5V -3.3V / -5V NECL Output Translator |
| NB100LVEP91MN | 2.5V / 3.3V Any Level Positive Input to -2.5V -3.3V / -5V NECL Output Translator |
| NB100LVEP91-D | 2.5V / 3.3V AnyLevel? Positive Input to -2.5V / -3.3V / -5V NECL Output Translator |
| NB100LVEP224FAR2 | 2.5V/3.3V 1:24 Differential ECL/PECL Clock Driver with Clock Select and Output Enable |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NB100LVEP91_06 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:2.5 V/3.3 V Any Level Positive Input to −2.5 V/−3.3 V LVNECL Output Translator |
| NB100LVEP91-D | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:2.5V / 3.3V AnyLevel? Positive Input to -2.5V / -3.3V / -5V NECL Output Translator |
| NB100LVEP91DW | 功能描述:轉(zhuǎn)換 - 電壓電平 2.5V/3.3V Any LVL to RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MLF-8 |
| NB100LVEP91DWG | 功能描述:轉(zhuǎn)換 - 電壓電平 2.5V/3.3V Any LVL to -2.5V/-3.3V/-5V NECL RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MLF-8 |
| NB100LVEP91DWR2 | 功能描述:轉(zhuǎn)換 - 電壓電平 2.5V/3.3V Any LVL to RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MLF-8 |
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