參數(shù)資料
型號: NB100LVEP224FAR2
廠商: ON SEMICONDUCTOR
元件分類: 時鐘及定時
英文描述: 2.5V/3.3V 1:24 Differential ECL/PECL Clock Driver with Clock Select and Output Enable
中文描述: 100LVE SERIES, LOW SKEW CLOCK DRIVER, 24 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP64
封裝: LQFP-64
文件頁數(shù): 1/14頁
文件大?。?/td> 153K
代理商: NB100LVEP224FAR2
Semiconductor Components Industries, LLC, 2004
December, 2004
Rev. 5
1
Publication Order Number:
NB100LVEP56/D
NB100LVEP56
2.5V / 3.3V / 5VECL Dual
Differential 2:1 Multiplexer
The NB100LVEP56 is a dual, fully differential 2:1 multiplexer. The
differential data path makes the device ideal for multiplexing low
skew clock or differential data signals. The device features both
individual and common select inputs to address both data path and
random logic applications. Common and individual selects can accept
both ECL and CMOS input voltage levels. Multiple V
BB
pins are
provided.
The V
BB
pin, an internally generated voltage supply, is available to
this device only. For single
ended input operation, the unused
differential input is connected to V
BB
as a switching reference voltage.
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a 0.01 F capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V
BB
should be left open.
Maximum Input Clock Frequency > 2.5 GHz Typical
Maximum Input Data Rate > 2.5 Gb/s Typical
525 ps Typical Propagation Delays
Low Profile QFN Package
PECL Mode Operating Range:
V
CC
= 2.375 V to 5.5 V with V
EE
= 0 V
NECL Mode Operating Range:
V
CC
= 0 V with V
EE
=
2.375 V to
5.5 V
Separate, Common Select, and Individual Select
(Compatible with ECL and CMOS Input Voltage Levels)
Q Output Will Default LOW with Inputs Open or at V
EE
Multiple V
BB
Outputs
Pb
Free Packages are Available*
*For additional information on our Pb
Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
TSSOP
20
DT SUFFIX
CASE 948E
MARKING
DIAGRAMS*
*For additional information, see Application Note
AND8002/D
N100
VP56
ALYW
20
1
1
20
A = Assembly Location
L
= Wafer Lot
Y = Year
W = Work Week
N100
VP56
ALYW
1
24
QFN
24
MN SUFFIX
CASE 485L
24
1
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
ORDERING INFORMATION
http://onsemi.com
相關(guān)PDF資料
PDF描述
NB2308A 3.3 V Zero Delay Clock Buffer(3.3V零延遲時鐘緩沖器)
NB2309A 3.3 V Zero Delay Clock Buffer(3.3V零延遲時鐘緩沖器)
NB2669A Low Power, Reduced EMI Clock Synthesizer(低功率,降低EMI時鐘合成器)
NB2760A Low Power, Reduced EMI Clock Synthesizer(低功率,降低EMI時鐘合成器)
NB2762A Low Power, Reduced EMI Clock Synthesizer(低功率,降低EMI時鐘合成器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
NB100LVEP224FARG 功能描述:時鐘驅(qū)動器及分配 BBG DIF ECL PECL CLD DRV RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel
NB100LVEP56 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:2.5V / 3.3V / 5VECL Dual Differential 2:1 Multiplexer
NB100LVEP56/D 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2.5 V / 3.3 V 5 V ECL Dual Differential 2:1 Multiplexer
NB100LVEP56_06 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:2.5V / 3.3V ECL DUAL Differential 2:1 Multiplexer
NB100LVEP56DT 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 2.5V/3.3V/5V ECL RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量(輸入/輸出):2 / 12 傳播延遲時間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray