參數(shù)資料
型號(hào)： NAND128W3A0AV6
廠商： 意法半導(dǎo)體
英文描述： 128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16) 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories
中文描述： 128兆，256兆，512兆位，1千兆位（x8/x16）528 Byte/264字的頁(yè)面，1.8V/3V，NAND閃存芯片
文件頁(yè)數(shù)： 56/57頁(yè)
文件大小： 916K
代理商： NAND128W3A0AV6
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
56/57
REVISION HISTORY
Table 29. Document Revision History
Date
Version
Revision Details
06-Jun-2003
1.0
First Issue
07-Aug-2003
2.0
Design Phase
27-Oct-2003
3.0
Engineering Phase
03-Dec-2003
4.0
Document promoted from Target Specification to Preliminary Data status.
V
CC
changed to V
DD
and I
CC
to I
DD
.
Title of
Table 2.
. changed to “
Product Description
” and Page Program Typical Timing
for NANDXXXR3A devices corrected.
Table 1., Product List
, inserted on page 2.
13-Apr-2004
5.0
WSOP48 and VFBGA55 packages added, VFBGA63 (9 x 11 x 1mm) removed.
Figure 19., Cache Program Operation
, modified and note 2 modified. Note removed
for t
WLWH
timing in
Table 20., AC Characteristics for Command, Address, Data Input
.
Meaning of t
BLBH4
modified, partly replaced by t
WHBH1
and t
WHRL
min for 3V devices
modified in
Table 21., AC Characteristics for Operations
.
References removed from
RELATED DOCUMENTATION
section and reference
made to ST Website instead.
Figure 6.
,
Figure 7.
,
Figure 29.
and
Figure 32.
modified.
Read Electronic Signature
paragraph clarified and
Figure 28., Read Electronic Signature AC Waveform
,
modified. Note 2 to
Figure 30., Read C Operation, One Page AC Waveform
, removed.
Note 3 to
Table 7., Address Insertion, x16 Devices
removed. Only 00h Pointer
operations are valid before a Cache Program operation. I
DD4
removed from
Table
18., DC Characteristics, 1.8V Devices
. Note added to
Figure 32., Block Erase AC
Waveform
. Small text changes.
28-May-2004
6.0
TFBGA55 package added (mechanical data to be announced). 512Mb Dual Die
devices added.
Figure 19., Cache Program Operation
modified.
Package code changed for TFBGA63 8.5 x 15 x 1.2mm, 6x8 ball array, 0.8mm pitch
(1Gbit Dual Die devices) in
Table 28., Ordering Information Scheme
.
02-Jul-2004
7.0
Cache Program removed from document. TFBGA55 package specifications added
(
Figure 40., TFBGA55 8 x 10mm - 6x8 active ball array - 0.80mm pitch, Package
Outline
and
Table 25., TFBGA55 8 x 10mm - 6x8 active ball array - 0.80mm pitch,
Package Mechanical Data
).
Test conditions modified for V
OL
and V
OH
parameters in
Table 19., DC Characteristics,
3V Devices
.
01-Oct-2004
8.0
Third part number corrected in
Table 1., Product List
. 512 Mbit Dual Die information
added to
Table 10., Copy Back Program Addresses
.
Block Erase
last address cycle
modified. Definition of a Bad Block modified in
Bad Block Management
paragraph.
RoHS COMPLIANCE
added to
SUMMARY DESCRIPTION
.
Figure 3., Logic Block
Diagram
modified.
Document promoted from Preliminary Data to Full Datasheet status.
03-Dec-2004
9.0
Automatic Page 0 Read at Power-Up option no longer available.
PC Demo board with simulation software removed from list of available development
tools.
Chip Enable (E)
paragraph clarified.
13-Dec-2004
10.0
R
ref
parameter added to
Table 16., Operating and AC Measurement Conditions
.
Description of the family clarified in the
SUMMARY DESCRIPTION
section.
25-Feb-2005
11.0
WSOP48 replaced with USOP48 package,
VFBGA63 (8.5 x 15 x 1mm) replaced with VFBGA63 (9 x 11 x 1mm) package,
TFBGA63 (8.5 x 15 x 1mm) replaced with TFBGA63 (9 x 11 x 1.2mm) package.
Changes to
Table 21.
,
Table 18.
and
Table 2.
相關(guān)PDF資料
PDF描述
NAND256R3A0AZB6 128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16) 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories
NAND128W4A0CZA6E 128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16) 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories
NAND128R4A2BZA1E 128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16) 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories
NAND01GW4A2BV1E 128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16) 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories
NAND128R3A2BV1E 128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16) 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
NAND128W3A0BN6E 功能描述:閃存 2.7-3.6V 128M(16Mx8) RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲(chǔ)類型:Flash 存儲(chǔ)容量:2 MB 結(jié)構(gòu):256 K x 8 定時(shí)類型: 接口類型:SPI 訪問(wèn)時(shí)間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel
NAND128W3A0BN6F 功能描述:閃存 NAND & S.MEDIA FLASH RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲(chǔ)類型:Flash 存儲(chǔ)容量:2 MB 結(jié)構(gòu):256 K x 8 定時(shí)類型: 接口類型:SPI 訪問(wèn)時(shí)間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel
NAND128W3A2BDI6 制造商:Micron Technology Inc 功能描述:NAND 制造商:Micron Technology Inc 功能描述:NAND - Gel-pak, waffle pack, wafer, diced wafer on film
NAND128W3A2BN6E 功能描述:閃存 NAND 128 MEG RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲(chǔ)類型:Flash 存儲(chǔ)容量:2 MB 結(jié)構(gòu):256 K x 8 定時(shí)類型: 接口類型:SPI 訪問(wèn)時(shí)間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel
NAND128W3A2BN6F 功能描述:閃存 NAND 128 MEG RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲(chǔ)類型:Flash 存儲(chǔ)容量:2 MB 結(jié)構(gòu):256 K x 8 定時(shí)類型: 接口類型:SPI 訪問(wèn)時(shí)間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel
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